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參數(shù)資料
| 型號： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 82/138頁 |
| 文件大小： | 784K |
| 代理商： | M68HC16Y1CFC |
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MOTOROLA
MC68HC16Y1
48
MC68HC16Y1TS/D
size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are
valid while the address strobe (AS) is asserted. The table below shows SIZ0 and SIZ1 encoding. The
read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only tran-
sitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for two
consecutive write cycles.
3.5.2 Function Codes
Function code signals FC[2:0] are automatically generated by the CPU16. The function codes can be
considered address extensions that automatically select one of eight address spaces to which an ad-
dress applies. These spaces are designated as either user or supervisor, and program or data spaces.
Because the CPU16 always operates in supervisor mode (FC2 always = 1), address spaces 0 to 3 are
not used. Address space 7 is designated CPU space. CPU space is used for control information not
normally associated with read or write bus cycles. Function codes are valid while AS is asserted.
3.5.3 Address Bus
Address bus signals ADDR[19:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted. Because the CPU16 in the MC68HC16Y1 does not drive ADDR[23:20],
these lines follow the logic state of ADDR19.
3.5.4 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and of many control
signals. It is asserted one-half clock after the beginning of a bus cycle.
3.5.5 Data Bus
Data bus signals DATA[15:0] comprise a bidirectional, non-multiplexed parallel bus that transfers data
to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During
a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For
a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The
MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.
3.5.6 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device
to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,
DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle
after the assertion of AS during a write cycle.
Table 13 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
0
1
Byte
1
0
Word
1
3 Byte
0
Long Word
Table 14 CPU16 Address Space Encoding
FC2
FC1
FC0
Address Space
1
0
Reserved
1
0
1
Data Space
1
0
Program Space
1
CPU Space
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