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參數(shù)資料
| 型號(hào)： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 14/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MOTOROLA
MC68HC16Y1
110
MC68HC16Y1TS/D
RWU — Receiver Wakeup
0 = Normal receiver operation (received data recognized)
1 = Wakeup mode enabled (received data ignored until awakened)
Setting RWU enables the wakeup function, which allows the SCI to ignore received data until awakened
by either an idle line or address mark (as determined by WAKE). When in wakeup mode, the receiver
status flags are not set, and interrupts are inhibited. This bit is cleared automatically (returned to normal
mode) when the receiver is awakened.
SBK — Send Break
0 = Normal operation
1 = Break frame(s) transmitted after completion of current frame
SBK provides the ability to transmit a break code from the SCI. If the SCI is transmitting when SBK is
set, it will transmit continuous frames of zeros after it completes the current frame, until SBK is cleared.
If SBK is toggled (one to zero in less than one frame interval), the transmitter sends only one or two
break frames before reverting to idle line or commencing to send data.
Each SCSR contains flags that show SCI operational conditions. These flags can be cleared either by
hardware or by a special acknowledgment sequence. The sequence consists of SCSR read with flags
set, followed by SCDR read (write in the case of TDRE and TC). A long-word read can consecutively
access both SCSR and SCDR. This action clears receive status flag bits that were set at the time of the
read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits,
but before the CPU has written or read register SCDR, the newly set status bit is not cleared — SCSR
must be read again with the bit set, and SCDR must be written or read before the status bit is cleared.
Reading either byte of SCSR causes all 16 bits to be accessed, and any status bit already set in either
byte will be cleared on a subsequent read or write of register SCDR.
TDRE — Transmit Data Register Empty Flag
0 = Register TDR still contains data to be sent to the transmit serial shifter.
1 = A new character may now be written to register TDR.
TDRE is set when the byte in register TDR is transferred to the transmit serial shifter. If TDRE is zero,
transfer has not occurred and a write to TDR will overwrite the previous value. New data is not trans-
mitted if TDR is written without first clearing TDRE.
TC — Transmit Complete Flag
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
TC is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or
queued breaks (logic zero). The interrupt may be cleared by reading SCSR when TC is set and then by
writing the transmit data register (TDR) of SCDR.
RDRF — Receive Data Register Full Flag
0 = Register RDR is empty or contains previously read data.
1 = Register RDR contains new data.
RDRF is set when the content of the receive serial shifter is transferred to the RDR. If one or more errors
are detected in the received word, flag(s) NF, FE, and/or PF are set within the same clock cycle.
SCSRA, SCSRB — SCI Status Register
$YFFC1C, $YFFC2C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
TDRE
TC
RDRF
RAF
IDLE
OR
NF
FE
PF
RESET:
0
1
0
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