參數(shù)資料
型號(hào)： M68HC16Y1CFC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP16
封裝： QFP-160
文件頁數(shù)： 8/138頁
文件大?。?/td> 784K
代理商： M68HC16Y1CFC
MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
105
7.2.2 SPI Registers
The programmer's model for the SPI consists of the MCCI global and pin control registers, the SPI con-
trol register (SPCR), the SPI status register (SPSR), and the SPI data register (SPSR). All SPI registers
can be read and written by the CPU. SPCR must be initialized before the SPI is enabled to ensure de-
fined operation. The SPI is enabled by setting the SPE bit in SPCR. Reset values are shown below each
register.
SPCR contains parameters for configuring the SPI. The CPU has read and write access to all control
bits, but the MCCI has read access only to all bits except SPE. Writing a new value to SPCR while the
SPI is enabled disrupts operation. Writing the same value into SPCR while the SPI is enabled has no
effect on SPI operation.
SPIE — SPI Interrupt Enable
0 = SPI interrupts disabled
1 = SPI interrupts enabled
SPE — SPI Enable
0 = SPI is disabled. SPI pins can be used for general-purpose I/O.
1 = SPI is enabled. Pins allocated by PMCPAR are controlled by the SPI.
WOMP — Wired-OR Mode for SPI Pins
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by DDRMC have open-drain drivers.
WOMP allows SPI pins to be connected for wired-OR operation, regardless of whether they are used
for general-purpose output or for SPI output. WOMP affects the pins whether the SPI is enabled or dis-
abled.
MSTR — Master/Slave Mode Select
0 = SPI is a slave device and only responds to externally generated serial data.
1 = SPI is system master and can initiate transmission to external SPI devices.
MSTR configures the SPI for either master or slave mode operation. This bit is cleared on reset and
may only be written by the CPU.
CPOL — Clock Polarity
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to
produce a desired clock/data relationship between master and slave devices.
CPHA — Clock Phase
0 = Data captured on the leading edge of SCK and changed on the following edge of SCK.
1 = Data is changed on the leading edge of SCK and captured on the following edge of SCK.
CPHA determines which edge of SCK causes data to change and which edge causes data to be cap-
tured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave
devices. CPHA is set at reset.
LSBF — Least Significant Bit First
0 = Serial data transfer starts with MSB
1 = Serial data transfer starts with LSB
SPCR — SPI Control Register
$YFFC38
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPIE
SPE
WOMP
MSTR
CPOL
CPHA
LSBF
SIZE
BAUD
RESET:
0
1
0
1
0
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