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參數(shù)資料
| 型號(hào)： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 128/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
9
2 CPU16
The CPU16 is a true 16-bit, high-speed device. It was designed to give M68HC11 users a path to higher
performance while maintaining maximum compatibility with existing systems.
2.1 Overview
Ease of programming is an important consideration in using a microcontroller. The CPU16 instruction
set is optimized for high performance. There are two 16-bit general-purpose accumulators and three
16-bit index registers. The CPU16 supports 8-bit (byte), 16-bit (word), and 32-bit (long-word) load and
store operations, as well as 16- and 32-bit signed fractional operations. Program diagnosis is enhanced
by a background debugging mode.
CPU16 memory space includes a 1 Mbyte data space and a 1 Mbyte program space. Twenty-bit ad-
dressing and transparent bank switching are used to implement extended memory. In addition, most
instructions automatically handle bank boundaries.
The CPU16 includes instructions and hardware to implement control-oriented digital signal processing
functions with a minimum of interfacing. A multiply and accumulate unit provides the capability to mul-
tiply signed 16-bit fractional numbers and store the resulting 32-bit fixed point product in a 36-bit accu-
mulator. Modulo addressing supports finite impulse response filters.
Use of high-level languages is increasing as controller applications become more complex and control
programs become larger. High-level languages aid rapid development of software, with less error, and
are readily portable. The CPU16 instruction set supports high-level languages.
2.2 M68HC11 Compatibility
CPU16 architecture is a superset of M68HC11 architecture. All M68HC11 resources are available in
the HC16. M68HC11 instructions are either directly implemented in the M68HC16, or have been re-
placed by instructions with an equivalent form — the instruction sets are source code compatible. Some
instructions are executed differently in the M68HC16. These instructions are mainly related to interrupt
and exception processing — M68HC11 code that processes interrupts, handles stack frames, or ma-
nipulates the condition code register must be rewritten.
Execution times and number of cycles for all instructions are different, so that cycle-related delays and
timed control routines may be affected.
The CPU16 also has several new or enhanced addressing modes. M68HC11 direct mode addressing
has been replaced by a special form of indexed addressing that uses the new IZ register and a reset
vector to provide greater flexibility.
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