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參數(shù)資料
| 型號(hào)： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 81/138頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
47
PITR contains the count value for the periodic timer. A zero value turns off the periodic timer. This reg-
ister can be read or written at any time.
PTP — Periodic Timer Prescaler Control
1 = Periodic timer clock prescaled by a value of 512
0 = Periodic timer clock not prescaled
The reset state of PTP is the complement of the state of the MODCLK signal during reset.
PITM[7:0] — Periodic Interrupt Timing Modulus Field
This is an 8-bit timing modulus. The period of the timer can be calculated as follows:
PIT Period = [(PITM)(Prescale)(4)]/EXTAL
where
PIT Period = Periodic interrupt timer period
PITM = Periodic interrupt timer register modulus (PITR[7:0])
EXTAL = Crystal frequency
Prescale = 512 or 1 depending on the state of the PTP bit in the PITR
3.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external de-
vices when the MC68HC16Y1 is operating in expanded modes. In fully expanded mode, the external
bus has 24 address lines and 16 data lines. In partially expanded mode, the external bus has 24 ad-
dress lines and 8 data lines. Because the CPU16 in the MC68HC16Y1 drives only 20 of the 24 IMB
address lines, ADDR[23:20] follow the output state of ADDR19.
The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data
transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). In fully expanded
mode, both 8-bit and 16-bit data ports can be accessed; in partially expanded mode, only 8-bit ports
can be accessed. Multiple bus cycles may be required for a transfer to an 8-bit port.
Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip select logic can be synchro-
nized with EBI transfers. Chip select logic can also provide internally-generated bus control signals for
these accesses. See 3.9 Chip Selects for more information.
3.5.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The
PITR — Periodic Interrupt Timer Register
$YFFA24
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PTP
PITM
RESET:
0
MODCLK
0
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