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參數(shù)資料
| 型號： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 85/138頁 |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MOTOROLA
MC68HC16Y1
50
MC68HC16Y1TS/D
Figure 6 Operand Byte Order
3.5.10 Operand Alignment
The data multiplexer establishes the necessary connections for different combinations of address and
data sizes. The multiplexer takes the two bytes of the 16-bit bus and routes them to their required po-
sitions. Positioning of bytes is determined by the size and address outputs. SIZ1 and SIZ0 indicate the
remaining number of bytes to be transferred during the current bus cycle. The number of bytes trans-
ferred is equal to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] in-
dicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the
byte offset from the base. Bear in mind the fact that ADDR[23:20] follow the state of ADDR19 in the
MC68HC16Y1.
3.5.11 Misaligned Operands
CPU16 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it
overlaps a word boundary. This is determined by the value of ADDR0. When ADDR0 = 0 (an even ad-
dress), the address is on a word and byte boundary. When ADDR0 = 1 (an odd address), the address
is on a byte boundary only. A byte operand is aligned at any address; a word or long-word operand is
misaligned at an odd address.
In the MC68HC16Y1, the largest amount of data that can be transferred by a single bus cycle is an
aligned word. If the MCU transfers a long-word operand via a 16-bit port, the most significant operand
word is transferred on the first bus cycle and the least significant operand word on a following bus cycle.
The CPU16 can perform misaligned word transfers. This capability makes it software compatible with
the MC68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word trans-
fers.
3.5.12 Operand Transfer Cases
The following table summarizes how operands are aligned for various types of transfers. OPn entries
are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1,
SIZ0, and ADDR0 for that bus cycle.
Operand
Byte Order
31
24
23
16
15
8
7
0
Long Word
OP0
OP1
OP2
OP3
Three Byte
OP0
OP1
OP2
Word
OP0
OP1
Byte
OP0
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