參數(shù)資料
型號: M68HC16Y1CFC
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP16
封裝: QFP-160
文件頁數(shù): 109/138頁
文件大小: 784K
代理商: M68HC16Y1CFC
MOTOROLA
MC68HC16Y1
72
MC68HC16Y1TS/D
TCR1P — TCR1 Prescaler Control
TCR2P — TCR2 Prescaler Control
EMU — Emulation Control
0 = TPU and RAM not in emulation mode (reset condition)
1 = TPU and RAM in emulation mode
T2CG — TCR2 Clock/Gate Control
0 = TCR2 pin used as clock source for TCR2 (reset condition)
1 = TCR2 pin used as gate of DIV8 clock for TCR2
STF — Stop Flag
0 = TPU operating (reset condition)
1 = TPU stopped
SUPV — Supervisor Data Space
0 = Assignable registers are unrestricted (FC2 is ignored).
1 = Assignable registers are restricted (FC2 is decoded; reset condition).
PSCK — Prescaler Clock
0 = DIV32 (system clock/32) is input to TCR1 prescaler.
1 = DIV4 (system clock/4) is input to TCR1 prescaler.
IARB — Interrupt Arbitration ID Bits
Each module that generates interrupts has an IARB field. The value in this field is used to arbitrate be-
tween simultaneous interrupt requests of the same priority. The reset value of all IARB fields other than
that of the SCIM is $0 (lowest priority), to prevent priority conflict during initialization. The IARB field
must be initialized to a value between $F (highest priority) and $1 (lowest priority), or subsequent inter-
rupt requests will be identified by the CPU as spurious.
TCR — Test Configuration Register
$YFFE02
This register is used for Motorola factory test only.
TCR1
015
PSCK
MUX
÷ 4
DIV4 CLOCK
÷ 32
DIV32 CLOCK
TCR1
PRESCALER
00
÷ 1
01
÷ 2
10
÷ 4
11
÷ 8
SYSTEM
CLOCK
1 – DIV4
0 – DIV32
PRESCALER CTL BLOCK 1
PRESCALER CTL BLOCK 2
DIGITAL
FILTER
EXTERNAL
TCR2 PIN
TCR2
(T2CG CONTROL BIT)
0 – A
1 – B
015
A
B
MUX
CONTROL
SYNCHRONIZER
TCR2
PRESCALER
00
÷ 1
01
÷ 2
10
÷ 4
11
÷ 8
INT CLK /8
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