參數(shù)資料
型號: M68HC16Y1CFC
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP16
封裝: QFP-160
文件頁數(shù): 77/138頁
文件大小: 784K
代理商: M68HC16Y1CFC
MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
43
Both writes must occur in the order listed prior to time-out, but any number of instructions can be exe-
cuted between the two writes.
Watchdog clock rate is affected by SWP and SWT in SYPCR.
When SWT[1:0] are modified, a watchdog service sequence must be performed before the new time-
out period will take effect.
The reset value of SWP is the complement of the state of the MODCLK pin on the rising edge of reset.
Software watchdog time-out period is given by the following equation:
Time-Out Period = Divide Count/EXTAL Frequency
3.4 System Clock
The system clock in the SCIM provides timing signals for the IMB modules and for an external peripheral
bus. Because the MC68HC16Y1 is a fully static design, register and memory contents are not affected
when clock rate changes. System hardware and software support changes in clock rate during opera-
tion.
The system clock signal can be generated in three ways. An internal phase-locked loop can synthesize
the clock from either an internal or an external frequency source, or the clock signal can be input from
an external source.
Following is a block diagram of the clock submodule.
Figure 5 System Clock Block Diagram
SYS CLOCK
BLOCK 32KHZ
CLKOUT
EXTAL
PHASE
COMPARATOR
LOW-PASS
FILTER
VCO
CRYSTAL
OSCILLATOR
SYSTEM
CLOCK
SYSTEM CLOCK CONTROL
XTAL
XFC PIN
VDDSYN
XFC
1
0.1
F
.01
F
0.1
F
FEEDBACK DIVIDER
22 pF
2
10M
330 k
W
X
Y
VSSI
22 pF
2
VSSI
VDDSYN
1. Must be low-leakage capacitor (insulation resistance 30,000 M
or greater).
2. Capacitance based on a test circuit constructed with a DAISHINKU DMX-38 32.768-kHz crystal.
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