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參數(shù)資料
| 型號： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 79/138頁 |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
45
The SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide
by a value of Y
+ 1. When either W or Y value changes, there is a VCO relock delay.
Clock frequency is determined by SYNCR bit settings as follows:
FSYSTEM = FREFERENCE [4(Y + 1)(2
2W + X)]
In order for the device to perform correctly, the clock frequency selected by the W, X, and Y bits must
be within the limits specified for the MCU. Maximum specified clock frequency with a 32.768 kHz refer-
ence is 16.78 kHz.
VCO frequency is determined by:
FVCO = FSYSTEM (2 – X), for 32.768 kHz devices.
The reset state of SYNCR ($3F00) produces a modulus-64 count.
3.4.3 Clock Control
The clock control circuits determine system clock frequency and clock operation under special circum-
stances, such as loss of synthesizer reference or low-power mode. Clock source is determined by the
logic state of the MODCLK pin during reset.
When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper
byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks.
Because the CPU16 always operates in supervisor mode, SYNCR can be read or written at any time.
W — Frequency Control (VCO)
This bit controls a prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO
speed by a factor of four. VCO relock delay is required.
X — Frequency Control Bit (Prescale)
This bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting it doubles
clock speed without changing VCO speed. There is no VCO relock delay.
Y[5:0] — Frequency Control (Counter)
The Y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by
a value of Y
+ 1. Values range from 0 to 63. VCO relock delay is required.
EDIV — E Clock Divide Rate
0 = ECLK frequency is system clock divided by 8.
1 = ECLK frequency is system clock divided by 16.
ECLK is an external M6800 bus clock available on pin ADDR23. See 3.9 Chip Selects for more infor-
mation.
SLIMP — Limp Mode Flag
0 = External crystal is VCO reference.
1 = Loss of crystal reference.
When the on-chip synthesizer is used, loss of reference frequency will cause SLIMP to be set. The VCO
continues to run using the base control voltage. Maximum limp frequency is maximum specified system
clock frequency. X-bit state affects limp frequency.
SYNCR — Clock Synthesizer Control Register
$YFFA04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
X
Y
EDIV
0
SLIMP
SLOCK RSTEN
STSCIM
STEXT
RESET:
0
1
0
U
0
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