參數(shù)資料
型號： M68HC16Y1CFC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP16
封裝： QFP-160
文件頁數(shù)： 111/138頁
文件大小： 784K
代理商： M68HC16Y1CFC
MOTOROLA
MC68HC16Y1
74
MC68HC16Y1TS/D
BKPT — Breakpoint Asserted Flag
If an internal breakpoint caused the TPU to enter the halted state, the TPU asserts the BKPT signal on
the IMB and the BKPT flag. The TPU continues to assert BKPT until it recognizes a breakpoint acknowl-
edge cycle from a host, or until the FREEZE signal on the IMB is asserted.
PCBK —
PC Breakpoint Flag
PCBK is asserted if a breakpoint occurs because of a
PC register match with the PC breakpoint reg-
ister. PCBK is negated when the BKPT flag is negated.
CHBK — Channel Register Breakpoint Flag
CHBK is asserted if a breakpoint occurs because of a CHAN register match with the channel register
breakpoint register. CHBK is negated when the BKPT flag is negated.
SRBK — Service Request Breakpoint Flag
SRBK is asserted if a breakpoint occurs because of any of the service request latches being asserted
along with their corresponding enable flag in the development support control register. SRBK is negated
when the BKPT flag is negated.
TPUF — TPU FREEZE Flag
TPUF is asserted whenever the TPU is in a halted state as a result of FREEZE being asserted. This
flag is automatically negated when the TPU exits the halted state because of FREEZE being negated.
TICR[15:11] — Not Implemented
CIRL — Channel Interrupt Request Level
The interrupt request level for all channels is specified by this three-bit encoded field. Level seven for
this field indicates a nonmaskable interrupt; level zero indicates that all channel interrupts are disabled.
CIBV — Channel Interrupt Base Vector
This field specifies the most significant nibble of all 16 TPU channel interrupt vector numbers.
TICR[3:0] — Not Implemented
CH[15:0] — Interrupt Enable/Disable for each Channel
0 = Channel interrupts disabled
1 = Channel interrupts enabled
CFSR[15:0] — Encoded One of 16 Time Functions for each Channel
TICR — TPU Interrupt Configuration Register
$YFFE08
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIRL
CIBV
0
RESET:
0
CIER — Channel Interrupt Enable Register
$YFFE0A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH 15
CH 14
CH 13
CH 12
CH 11
CH 10
CH 9
CH 8
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
RESET:
0
CFSR0–CFSR3 — Channel Function Select Registers
$YFFE0C–$YFFE12
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH (15) (11) (7) (3)
CH (14) (10) (6) (2)
CH (3) (9) (5) (1)
CH (12) (8) (4) (0)
RESET:
0
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