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參數(shù)資料
| 型號(hào)： | M58WR064KU70ZA6U |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁(yè)數(shù)： | 70/122頁(yè) |
| 文件大?。?/td> | 2187K |
| 代理商： | M58WR064KU70ZA6U |
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M58WRxxxKU, M58WRxxxKL
Read modes
51/123
9.2
Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It
is possible to perform burst reads across bank boundaries.
Synchronous burst read mode can only be used to read the memory array. For other read
operations, such as read status register, read CFI, and read electronic signature, use single
synchronous read or asynchronous random access read.
In synchronous burst read mode the flow of the data output depends on parameters that are
configured in the configuration register.
A burst sequence is started at the first clock edge (rising or falling depending on valid clock
edge bit CR6 in the configuration register) after the falling edge of Latch Enable. Addresses
are internally incremented and after a delay of 2 to 5 clock cycles (X- latency bits CR13-
CR11) the corresponding data is output on each clock cycle.
The number of words to be output during a synchronous burst read operation can be
configured as 4, 8 or 16 words or continuous (burst length bits CR2-CR0). The data can be
configured to remain valid for one or two clock cycles (data output configuration bit CR9).
The order of the data output can be modified through the burst type and the wrap burst bits
in the configuration register. The burst sequence may be configured to be sequential or
interleaved (CR7). The burst reads can be confined inside the 4-, 8-, or 16-word boundary
(wrap) or overcome the boundary (no wrap). If the starting address is aligned to the burst
length (4, 8 or 16 words), the wrapped configuration has no impact on the output sequence.
Interleaved mode is not allowed in continuous burst read mode or with no wrap sequences.
A WAIT signal may be asserted to indicate to the system that an output delay occurs. This
delay depends on the starting address of the burst sequence; the worst case delay occurs
when the sequence is crossing a 16-word boundary and the starting address is at the end of
a 4-word boundary.
WAIT is asserted during X-latency, the Wait state and at the end of a 4-, 8-, and 16-word
burst. It is only deasserted when output data is valid or when G is at VIH. In continuous burst
read mode a Wait state occurs when crossing the first 16-word boundary. If the burst
starting address is aligned to a 4-word page, the Wait state does not occur.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
configuration register.
AC waveforms for details.
Synchronous burst read suspend
A synchronous burst read operation can be suspended, freeing the data bus for other higher
priority devices. It can be suspended during the initial access latency time (before data is
output) or after the device has output data. When the synchronous burst read operation is
suspended, internal array sensing continues and any previously latched internal data is
retained. A burst sequence can be suspended and resumed as often as required as long as
the operating conditions of the device are met.
A synchronous burst read operation is suspended when E is low and the current address
has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal
is then halted at VIH or at VIL, and G goes high.
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| M5L28FGNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L13TCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L14FCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L15TGNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M5L13TCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T100ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T85ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR128EB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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