參數(shù)資料
型號： M58WR064KU70ZA6U
廠商： NUMONYX
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝： 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件頁數(shù)： 33/122頁
文件大?。?/td> 2187K
代理商： M58WR064KU70ZA6U
Signal descriptions
M58WRxxxKU, M58WRxxxKL
2.7
Reset/Power-down (RP)
The Reset/Power-down input provides a hardware reset of the memory, and/or power-down
functions, depending on the settings in the configuration register. When Reset/Power-Down
is at VIL, the memory is in reset mode: the outputs are high impedance and the current
consumption is reduced to the standby supply current IDD3, or to the reset/power-down
supply current IDD2 if the power-down function is enabled. Refer to Table 22: DC
characteristics - currents for the value of IDD2 and IDD3.
After reset all blocks are in the locked state and the bits of the configuration register are
reset except for power-down bit CR5. When Reset/Power-down is at VIH, the device is in
normal operation. Upon exiting reset mode the device enters asynchronous read mode, but
a negative transition of Chip Enable or Latch Enable is required to ensure valid data
outputs.
2.8
Latch Enable (L)
Latch Enable latches the ADQ0-ADQ15 and A16-Amax address bits on its rising edge. The
address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch
Enable is at VIH.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is ‘don't care ‘during
asynchronous read and in write operations.
2.10
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is
at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.
The WAIT signal is forced deasserted when Output Enable is at VIH.
2.11
Bus Invert (BINV)
Bus Invert is an input/output signal that reduces the amount of power required to switch the
external address/data bus. Power is saved by inverting the data on ADQ0-ADQ15 each time
the inversion results in a reduced number of pin transitions. Data is inverted when BINV is at
VIH (for example, if the data is AAAAh and BINV is at VIH, AAAAh becomes 5555h). BINV is
high impedance when Chip Enable or Output Enable is at VIH or when Reset/Power-down is
at VIL.
2.12
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58WR064T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory
M58WR064T100ZB6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory
M58WR064T70ZB6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory
M58WR064T85ZB6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory
M58WR128EB 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
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