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參數(shù)資料
| 型號(hào)： | M58WR064KU70ZA6U |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁(yè)數(shù)： | 122/122頁(yè) |
| 文件大?。?/td> | 2187K |
| 代理商： | M58WR064KU70ZA6U |
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M58WRxxxKU, M58WRxxxKL
Common flash interface
99/123
1.
The variable P is a pointer that is defined at CFI offset 15h.
2.
Table 42.
Protection register information(1)
Offset
Data
Description
Value
(P+E)h = 47h
0001h
Number of protection register fields in JEDEC ID space. 0000h indicates
that 256 fields are available.
1
(P+F)h = 48h
0080h
Protection Field 1: protection description
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
0080h
(P+10)h = 49h
0000h
(P+11)h =
4Ah
0003h
8 Bytes
(P+12)h= 4Bh
0004h
16 Bytes
1.
The variable P is a pointer that is defined at CFI offset 15h.
Table 43.
Burst read Information(1)
Offset
Data
Description
Value
(P+13)h = 4Ch
0003h
Page-mode read capability
bits 0-7’n’ such that 2n HEX value represents the number of read-page
bytes. See offset 28h for device word width to determine page-mode data
output width.
8 Bytes
(P+14)h = 4Dh
0004h
Number of synchronous mode read configuration fields that follow.
4
(P+15)h = 4Eh
0001h
Synchronous mode read capability configuration 1
bit 3-7Reserved
bit 0-2’n’ such that 2n+1 HEX value represents the maximum number of
continuous synchronous reads when the device is configured for its
maximum word width. A value of 07h indicates that the device is capable of
continuous linear bursts that will output data until the internal burst counter
reaches the end of the device’s burstable address space. This field’s 3-bit
value can be written directly to the read configuration register bit 0-2 if the
device is configured for its maximum word width. See offset 28h for word
width to determine the burst data output width.
4
(P+16)h = 4Fh
0002h
Synchronous mode read capability configuration 2
8
(P+17)h = 50h
0003h
Synchronous mode read capability configuration 3
16
(P+18)h = 51h
0007h
Synchronous mode read capability configuration 4
Cont.
1.
The variable P is a pointer that is defined at CFI offset 15h.
Table 44.
Bank and erase block region information
M58WR032KU
M58WR032KL
Description
Offset
Data
Offset
Data
(P+19)h = 52h
02h
(P+19)h = 52h
02h
Number of Bank Regions within the device
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PDF描述 |
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| M5L28FGNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L13TCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L14FCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M3L15TGNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
| M5L13TCNFREQ | CRYSTAL OSCILLATOR, CLOCK, 1.544 MHz - 125 MHz, HCMOS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T100ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T85ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR128EB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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