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參數(shù)資料
| 型號(hào)： | M58WR064KU70ZA6U |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁(yè)數(shù)： | 52/122頁(yè) |
| 文件大?。?/td> | 2187K |
| 代理商： | M58WR064KU70ZA6U |
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M58WRxxxKU, M58WRxxxKL
Command interface - factory program commands
35/123
6.4
Quadruple Enhanced Factory Program command
The Quadruple Enhanced Factory Program command programs one or more pages of four
adjacent words in parallel. The four words must differ only for the addresses ADQ0 and
ADQ1. VPP must be set to VPPH during Quadruple Enhanced Factory Program. If the block
is protected then the quadruple enhanced factory program operation aborts, the data in the
block does not change, and the status register outputs the error.
It has four phases: the setup phase, the load phase where the data is loaded into the buffer,
the combined program and verify phase where the loaded data is programmed to the
memory and then automatically checked and reprogrammed if necessary and the exit
phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the
verify phase. The load phase and the program and verify phase can be repeated to program
any number of pages within the block.
6.4.1
Setup phase
The Quadruple Enhanced Factory Program command requires one bus write operation to
initiate the load phase. After the setup command is issued, read operations output the status
register data. The Read Status Register command must not be issued or it is interpreted as
data to program.
6.4.2
Load phase
The load phase requires 4 cycles to load the data (refer to Table 9: Factory program
commands and Figure 29: Quadruple enhanced factory program flowchart). Once the first
word of each page is written it is impossible to exit the load phase until all four words have
been written.
Two successive steps are required to issue and execute the load phase of the Quadruple
Enhanced Factory Program command.
1.
Use one bus write operation to latch the start address and the first word of the first
page to be programmed. For subsequent pages the first word address can remain the
start address (in which case the next page is programmed) or can be any address in
the same block. If any address with data FFFFh is given that is not in the same block
as the start address, the device enters the exit phase. For the first load phase status
register bit SR7 should be read after the first word has been issued to check that the
command has been accepted (bit SR7 set to ‘0’). This check is not required for
subsequent load phases.
2.
Each subsequent word to be programmed is latched with a new bus write operation.
The address is only checked for the first word of each page as the order of the words to
be programmed is fixed.
The memory is now set to enter the program and verify phase.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T100ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T85ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR128EB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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