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參數(shù)資料
| 型號： | M58WR064KU70ZA6U |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁數(shù)： | 41/122頁 |
| 文件大?。?/td> | 2187K |
| 代理商： | M58WR064KU70ZA6U |
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M58WRxxxKU, M58WRxxxKL
Command interface - standard commands
25/123
5.6
Block Erase command
The Block Erase command erases a block by setting all the bits within the selected block to
’1’. All previous data in the block is lost. If the block is protected then the erase operation
aborts, the data in the block does not change, and the status register outputs the error. The
Block Erase command can be issued at any moment regardless of whether the block has
been programmed or not.
Two bus write cycles are required to issue the command.
●
The first bus cycle sets up the erase command.
●
The second latches the block address in the program/erase controller and starts it.
If the second bus cycle is not Write Erase Confirm (D0h), status register bits SR4 and SR5
are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot
be guaranteed when the erase operation aborts, the block must be erased again.
Once the Block Erase command is issued the device outputs the status register data when
any address within the bank is read. At the end of the operation the bank remains in read
status register mode until a Read Array, Read CFI Query or Read Electronic Signature
command is issued.
During erase operations the bank containing the block being erased only accepts the Read
Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend commands: all other commands are ignored. Refer to Section 10:
Dual operations and multiple bank architecture for detailed information about simultaneous
operations allowed in banks not being erased. Typical erase times are given in Table 18:
See Appendix C, Figure 24: Block erase flowchart and pseudocode for a suggested
flowchart for using the Block Erase command.
5.7
Program command
The memory array can be programmed word-by-word. Only one word in one bank can be
programmed at any one time. If the block is protected then the program operation aborts,
the data in the block does not changed, and the status register outputs the error.
Two bus write cycles are required to issue the Program command.
●
The first bus cycle sets up the Program command.
●
The second latches the address and the data to be written and starts the
program/erase controller.
After programming has started, read operations in the bank being programmed output the
status register content.
During program operations the bank being programmed only accepts the Read Array, Read
Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend commands. Refer to Section 10: Dual operations and multiple bank architecture
for detailed information about simultaneous operations allowed in banks not being
programmed. Typical program times are given in Table 18: Program and erase times and
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the memory location must be reprogrammed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T100ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T70ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR064T85ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory |
| M58WR128EB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory |
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