參數(shù)資料
型號(hào): LAN9116-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類(lèi): 微控制器/微處理器
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁(yè)數(shù): 91/126頁(yè)
文件大?。?/td> 831K
代理商: LAN9116-MT
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
91
Revision 1.1 (05-17-05)
DATASHEET
5.3.24
E2P_DATA – EEPROM Data Register
This register is used in conjunction with the E2P_CMD register to perform read and write operations
with the Serial EEPROM
5.4
MAC Control and Status Registers
These registers are located in the MAC module and are accessed indirectly through the MAC-CSR
synchronizer port.
Table 5.6, "LAN9116 MAC CSR Register Map"
, shown below, lists the MAC registers
that are accessible through the indexing method using the MAC_CSR_CMD and MAC_CSR_DATA
registers (see sections MAC_CSR_CMD – MAC CSR Synchronizer Command Register and
MAC_CSR_DATA – MAC CSR Synchronizer Data Register).
9
EPC Time-out.
If an EEPROM operation is performed, and there is no
response from the EEPROM within 30mS, the EEPROM controller will time-
out and return to its idle state. This bit is set when a time-out occurs
indicating that the last operation was unsuccessful.
Note:
If the EEDIO signal pin is externally pulled-high, EPC commands
will not time out if the EEPROM device is missing. In this case the
EPC Busy bit will be cleared as soon as the command sequence
is complete. It should also be noted that the ERASE, ERAL,
WRITE and WRAL commands are the only EPC commands that
will time-out if an EEPROM device is not present -
and-
the EEDIO
signal is pulled low
R/WC
0
8
MAC Address Loaded.
When set, this bit indicates that a valid EEPROM
was found, and that the MAC address programming has completed
normally. This bit is set after a successful load of the MAC address after
power-up, or after a RELOAD command has completed
RO
-
7-0
EPC Address.
The 8-bit value in this field is used by the EEPROM
Controller to address the specific memory location in the Serial EEPROM.
This is a Byte aligned address.
R/W
00h
Offset:
B4h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31-8
Reserved.
RO
-
7:0
EEPROM Data.
Value read from or written to the EEPROM.
R/W
00h
BITS
DESCRIPTION
TYPE
DEFAULT
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