參數(shù)資料
型號: LAN9116-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 114/126頁
文件大小: 831K
代理商: LAN9116-MT
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
114
SMSC LAN9116
DATASHEET
Note:
The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note:
A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
6.4
RX Data FIFO Direct PIO Reads
In this mode the upper address inputs are not decoded, and any read of the LAN9116 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9116. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit Direct PIO Read cycles is identical with the exception that D[31:16] is not
driven during a 16-bit read. Note that address lines A[2:1] are still used, and address bits A[7:3] are
ignored.
Table 6.4 PIO Burst Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
csh
nCS, nRD Deassertion Time
13
ns
t
csdv
nCS, nRD Valid to Data Valid
30
ns
t
acyc
Address Cycle Time
165
t
asu
Address Setup to nCS, nRD valid
0
ns
t
adv
Address Stable to Data Valid
40
t
ah
Address Hold Time
0
ns
t
don
Data Buffer Turn On Time
0
ns
t
doff
Data Buffer Turn Off Time
7
ns
t
doh
Data Output Hold Time
0
ns
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