- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359605 > LAN9116-MT (STANDARD MICROSYSTEMS CORP) Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | LAN9116-MT |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | ROHS COMPLIANT, TQFP-100 |
| 文件頁數(shù)： | 70/126頁 |
| 文件大小： | 831K |
| 代理商： | LAN9116-MT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁當(dāng)前第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
70
SMSC LAN9116
DATASHEET
5.3.3
INT_STS—Interrupt Status Register
This register contains the current status of the generated interrupts. Writing a 1 to the corresponding
bits acknowledges and clears the interrupt.
Offset:
58h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
Software Interrupt (SW_INT).
This interrupt is generated when the
SW_INT_EN bit is set high. Writing a one clears this interrupt.
R/WC
0
30-26
Reserved
RO
-
25
TX Stopped (TXSTOP_INT).
This interrupt is issued when STOP_TX bit
in TX_CFG is set, and the transmitter is halted.
R/WC
0
24
RX Stopped (RXSTOP_INT).
T
his interrupt is issued when the receiver is
halted.
R/WC
0
23
RX Dropped Frame Counter Halfway (RXDFH_INT).
This interrupt is
issued when the RX Dropped Frames Counter counts past its halfway
point (7FFFFFFFh to 80000000h).
R/WC
0
22
Reserved
RO
0
21
TX IOC Interrupt (TX_IOC).
When a buffer with the IOC flag set has
finished being loaded into the TX FIFO, this interrupt is generated.
R/WC
0
20
RX DMA Interrupt (RXD_INT).
This interrupt is issued when the amount
of data programmed in the RX DMA Count (RX_DMA_CNT) field of the
RX_CFG register has been transferred out of the RX FIFO.
R/WC
0
19
GP Timer (GPT_INT).
This interrupt is issued when the General Purpose
timer wraps past zero to FFFFh.
R/WC
0
18
PHY (PHY_INT).
Indicates a PHY Interrupt event.
RO
0
17
Power Management Event Interrupt (PME_INT).
This interrupt is issued
when a Power Management Event is detected as configured in the
PMT_CTRL register. This interrupt functions independent of the PME
signal, and will still function if the PME signal is disabled. Writing a '1'
clears this bit regardless of the state of the PME hardware signal.
Notes:
■
Detection of a Power Management Event, and assertion of the PME
signal will not wakeup the LAN9116. The LAN9116 will only wake up
when it detects a host write cycle of any data to the BYTE_TEST
register.
■
The Interrupt Deassertion interval does not apply to the PME interrupt.
R/WC
0
16
TX Status FIFO Overflow (TXSO).
Generated when the TX Status
FIFO overflows.
R/WC
0
15
Receive Watchdog Time-out (RWT).
Interrupt is generated when a
packet larger than 2048 bytes has been received.
R/WC
0
14
Receiver Error (RXE).
Indicates that the receiver has encountered an
error. Please refer to
Section 3.13.5, "Receiver Errors," on page 56
for a
description of the conditions that will cause an RXE.
R/WC
0
13
Transmitter Error (TXE).
When generated, indicates that the
transmitter has encountered an error. Please refer to
Section 3.12.8,
"Transmitter Errors," on page 51
, for a description of the conditions that
will cause a TXE.
R/WC
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LP621024D-55LLT | 128K X 8 BIT CMOS SRAM |
| LP621024D-I | 128K X 8 BIT CMOS SRAM |
| LP621024D-T | 128K X 8 BIT CMOS SRAM |
| LP62S1024BM-70LLT | 128K X 8 BIT LOW VOLTAGE CMOS SRAM |
| LP621024DX-55LLI | 128K X 8 BIT CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LAN9117 | 制造商:SMSC 制造商全稱:SMSC 功能描述:HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER |
| LAN9117-MD | 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN9117-MT | 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN9118 | 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller |
| LAN9118_05 | 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。