參數(shù)資料
型號: LAN9116-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 32/126頁
文件大?。?/td> 831K
代理商: LAN9116-MT
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
32
SMSC LAN9116
DATASHEET
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
3.9.2.1
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
page 89
for E2P_CMD field settings for each command.
ERASE (Erase Location):
If erase/write operations are enabled in the EEPROM, this command will
erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the
EEPROM does not respond within 30ms.
Figure 3.3 EEPROM Access Flow Diagram
Idle
Write Data
Register
Write
Command
Register
Read
Command
Register
Busy Bit = 0
Idle
Write
Command
Register
Read
Command
Register
Read Data
Register
Busy Bit = 0
EEPROM Write
EEPROM Read
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