參數(shù)資料
型號： LAN9116-MT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： ROHS COMPLIANT, TQFP-100
文件頁數(shù)： 67/126頁
文件大?。?/td> 831K
代理商： LAN9116-MT
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.2.2
SMSC LAN9116
67
Revision 1.1 (05-17-05)
DATASHEET
TX FIFO Ports
The TX data Path consists of two FIFOs, the TX status and data. The TX Status FIFO can be read
from two locations. The TX Status FIFO Port will perform a destructive read, thus “Popping” the data
from the TX Status FIFO. There is also the TX Status FIFO PEEK location. This location allows a non-
destructive read of the top (oldest) location of the FIFO.
The TX data FIFO is Write Only. It is aliased in 8 DWORD locations (16 WORD locations in 16-bit
mode) from the 20h offset to 3Ch offset. The host may write to any of the 8(16) locations since they
all access the same TX data FIFO location and perform the same function.
5.3
System Control and Status Registers
Table 5.1, "LAN9116 Direct Address Register Map"
, lists the registers that are directly addressable by
the host bus.
Table 5.1 LAN9116 Direct Address Register Map
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET
SYMBOL
REGISTER NAME
DEFAULT
50h
ID_REV
Chip ID and Revision.
See “ID_REV—
Chip ID and
Revision” on
page 68.
54h
IRQ_CFG
Main Interrupt Configuration
00000000h
58h
INT_STS
Interrupt Status
00000000h
5Ch
INT_EN
Interrupt Enable Register
00000000h
60h
RESERVED
Reserved for future use
-
64h
BYTE_TEST
Read-only byte order testing register
87654321h
68h
FIFO_INT
FIFO Level Interrupts
48000000h
6Ch
RX_CFG
Receive Configuration
00000000h
70h
TX_CFG
Transmit Configuration
00000000h
74h
HW_CFG
Hardware Configuration
00000800h
78h
RX_DP_CTL
RX Datapath Control
00000000h
7Ch
RX_FIFO_INF
Receive FIFO Information
00000000h
80h
TX_FIFO_INF
Transmit FIFO Information
00001200h
84h
PMT_CTRL
Power Management Control
00000000h
88h
GPIO_CFG
General Purpose IO Configuration
00000000h
8Ch
GPT_CFG
General Purpose Timer Configuration
0000FFFFh
90h
GPT_CNT
General Purpose Timer Count
0000FFFFh
94h
RESERVED
Reserved for future use
-
98h
ENDIAN
ENDIAN
00000000h
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