參數(shù)資料
型號： LAN9116-MT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： ROHS COMPLIANT, TQFP-100
文件頁數(shù)： 76/126頁
文件大小： 831K
代理商： LAN9116-MT
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
76
SMSC LAN9116
DATASHEET
15-14
Reserved
RO
-
13-12
Threshold Control Bits (TR).
These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
R/W
00
11-3
Reserved
RO
-
2
32/16-bit Mode.
When set, the LAN9116 is set for 32-bit operation. When
clear, it is configured for 16-bit operation. This field is the value of the
D32/nD16 strap.
RO
-
1
Soft Reset Time-out (SRST_TO)
. If a software reset is attempted when the
internal PHY is not in the operational state (RX_CLK and TX_CLK running),
the reset will not complete and the soft reset operation will time-out and this
bit will be set to a ‘1’. The host processor must correct the problem and
issue another soft reset.
RO
0
0
Soft Reset (SRST)
. Writing 1 generates a software initiated reset. This reset
generates a full reset of the MAC CSR’s. The SCSR’s (system command
and status registers) are reset except for any NASR bits. Soft reset also
clears any TX or RX errors (TXE/RXE). This bit is self-clearing.
Notes:
■
Do not attempt a soft reset unless the internal PHY is fully awake and
operational. After a PHY reset, or when returning from a reduced power
state, the PHY must be given adequate time to return to the operational
state before a soft reset can be issued. The internal RX_CLK and TX_CLK
signals must be running for a proper software reset. Please refer to
Section 6.8, "Reset Timing," on page 119
for details on PHY reset timing.
■
The LAN9116 must always be read at least once after power-up, reset, or
upon return from a power-saving state or write operations will not function.
SC
0
BITS
DESCRIPTION
TYPE
DEFAULT
[13]
[12]
Threshold (DWORDS)
0
0
012h
0
1
018h
1
0
020h
1
1
028h
[13]
[12]
Threshold (DWORDS)
0
0
020h
0
1
040h
1
0
080h
1
1
100h
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