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參數(shù)資料
| 型號(hào)： | LAN9116-MT |
| 廠(chǎng)商： | STANDARD MICROSYSTEMS CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | ROHS COMPLIANT, TQFP-100 |
| 文件頁(yè)數(shù)： | 52/126頁(yè) |
| 文件大?。?/td> | 831K |
| 代理商： | LAN9116-MT |
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
52
SMSC LAN9116
DATASHEET
The host must use caution when reading the RX data and status. The host must never read more data
than what is available in the FIFOs. If this is attempted an underrun condition will occur. If this error
occurs, the Ethernet controller will assert the Receiver Error (RXE) interrupt. If an underrun condition
occurs, a soft reset is required to regain host synchronization.
A configurable beginning offset is supported in the LAN9116. The RX data Offset field in the RX_CFG
register controls the number of bytes that the beginning of the RX data buffer is shifted. The host can
set an offset from 0-31 bytes. The offset may be changed in between RX packets, but it must not be
changed during an RX packet read.
The LAN9116 can be programmed to add padding at the end of a receive packet in the event that the
end of the packet does not align with the host burst boundary. This feature is necessary when the
LAN9116 is operating in a system that always performs multi-DWORD bursts. In such cases the
LAN9116 must guarantee that it can transfer data in multiples of the Burst length regardless of the
actual packet length. When configured to do so, the LAN9116 will add extra data at the end of the
packet to allow the host to perform the necessary number of reads so that the Burst length is not cut
short. Once a packet has been padded by the H/W, it is the responsibility of the host to interrogate the
Packet length field in the RX status and determine how much padding to discard at the end of the
Packet.
It is possible to read multiple packets out of the RX data FIFO in one continuous stream. It should be
noted that the programmed Offset and Padding will be added to each individual packet in the stream,
since packet boundaries are maintained.
3.13.1
RX Slave PIO Operation
Using PIO mode, the host can either implement a polling or interrupt scheme to empty the received
packet out of the RX data FIFO. The host will remain in the idle state until it receives an indication
(interrupt or polling) that data is available in the RX data FIFO. The host will then read the RX status
FIFO to get the packet status, which will contain the packet length and any other status information.
The host should perform the proper number of reads, as indicated by the packet length
plus
the start
offset
and
the amount of optional padding added to the end of the frame, from the RX data FIFO.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LAN9117 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER |
| LAN9117-MD | 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN9117-MT | 功能描述:以太網(wǎng) IC HiPerfrm Sngl-Chip 10/100 Ethrnt RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN9118 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller |
| LAN9118_05 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:High Performance Single-Chip 10/100 Non-PCI Ethernet Controller |
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