參數(shù)資料
型號: LAN9116-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 19/126頁
文件大?。?/td> 831K
代理商: LAN9116-MT
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
19
Revision 1.1 (05-17-05)
DATASHEET
Note 2.1
Please refer to the SMSC application note AN 12.5 titled “Designing with the LAN9118 -
Getting Started”. It is also important to note that this application note applies to the whole
SMSC LAN9118 family of Ethernet controllers. However, subtle differences may apply.
10
RBIAS
RBIAS
AI
1
PLL Bias:
Connect to an external
12.0K ohm 1.0% resistor to ground.
Used for the PLL Bias circuit.
9
Test Pin
ATEST
I
1
This pin must be connected to VDD
for normal operation.
2
Internal Regulator
Power
VREG
P
1
3.3V input for internal voltage
regulator
20,28,
35,
42,48,
55,61,
97
+3.3V I/O Power
VDD_IO
P
8
+3.3V I/O logic power supply pins
19,27,
34,41,
47,54,
60,96
I/O Ground
GND_IO
P
8
Ground for I/O pins
81,85,
89
+3.3V Analog
Power
VDD_A
P
3
+3.3V Analog power supply pins. See
Note 2.1
77,80,
86,88
Analog Ground
VSS_A
P
4
Ground for analog circuitry
3,65
Core Voltage
Decoupling
VDD_CORE
P
2
1.8 V from internal core regulator.
Both pins must be connected
together externally and then tied to a
10uF 0.1-Ohm ESR capacitor, in
parallel with a 0.01uF capacitor to
Ground next to each pin. See
Note 2.1
1,66
Core Ground
GND_CORE
P
2
Ground for internal digital logic
7
PLL Power
VDD_PLL
P
1
1.8V Power from the internal PLL
regulator. This external pin must be
connected to a 10uF 0.1-Ohm ESR
capacitor, in parallel with a 0.01uF
capacitor to Ground. See
Note 2.1
4
PLL Ground
VSS_PLL
P
1
GND for the PLL
8
Reference Power
VDD_REF
P
1
Connected to 3.3v power and used
as the reference voltage for the
internal PLL
11
Reference Ground
VSS_REF
P
1
Ground for internal PLL reference
voltage
Table 2.5 System and Power Signals (continued)
PIN
NO.
NAME
SYMBOL
BUFFER
TYPE
NUM
PINS
DESCRIPTION
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