參數(shù)資料
型號: LAN9116-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 115/126頁
文件大?。?/td> 831K
代理商: LAN9116-MT
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9116
115
Revision 1.1 (05-17-05)
DATASHEET
Note:
The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note:
An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
6.5
RX Data FIFO Direct PIO Burst Reads
In this mode the upper address inputs are not decoded, and any burst read of the LAN9116 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9116. Timing
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Table 6.5 RX Data FIFO Direct PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
cycle
Read Cycle Time
165
ns
t
csl
nCS, nRD Assertion Time
32
ns
t
csh
nCS, nRD Deassertion Time
13
ns
t
csdv
nCS, nRD Valid to Data Valid
30
ns
t
asu
Address, FIFO_SEL Setup to nCS, nRD Valid
0
ns
t
ah
Address, FIFO_SEL Hold Time
0
ns
t
don
Data Buffer Turn On Time
0
ns
t
doff
Data Buffer Turn Off Time
7
ns
t
doh
Data Output Hold Time
0
ns
Data Bus
nCS, nRD
FIFO_SEL
A[2:1]
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