參數(shù)資料
型號: LAN9116-MT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁數(shù): 72/126頁
文件大?。?/td> 831K
代理商: LAN9116-MT
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
72
SMSC LAN9116
DATASHEET
5.3.5
BYTE_TEST—Byte Order Test Register
This register can be used to determine the byte ordering of the current configuration
18
PHY (PHY_INT_EN)
R/W
0
17
Power Management Event Interrupt Enable (PME_INT_EN)
R/W
0
16
TX Status FIFO Overflow (TXSO_EN)
R/W
0
15
Receive Watchdog Time-out Interrupt (RWT_INT_EN)
R/W
0
14
Receiver Error Interrupt (RXE_INT_EN)
R/W
0
13
Transmitter Error Interrupt (TXE_INT_EN)
R/W
0
12
Reserved
RO
-
11
TX Data FIFO Underrun Interrupt (TDFU_INT_EN)
R/W
0
10
TX Data FIFO Overrun Interrupt (TDFO_INT_EN)
R/W
0
9
TX Data FIFO Available Interrupt (TDFA_INT_EN)
R/W
0
8
TX Status FIFO Full Interrupt (TSFF_INT_EN)
R/W
0
7
TX Status FIFO Level Interrupt (TSFL_INT_EN)
R/W
0
6
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
R/W
0
5
RX Data FIFO Level Interrupt (RDFL_INT_EN)
R/W
0
4
RX Status FIFO Full Interrupt (RSFF_INT_EN)
R/W
0
3
RX Status FIFO Level Interrupt (RSFL_INT_EN)
R/W
0
2-0
GPIO [2:0] (GPIOx_INT_EN).
R/W
000
Offset:
64h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:0
Byte Test
RO
87654321h
BITS
DESCRIPTION
TYPE
DEFAULT
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