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參數(shù)資料
| 型號(hào)： | LAN83C175 |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Ethernet CARDBUS Integrated Controller With Modem Support |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, TQFP-208 |
| 文件頁(yè)數(shù)： | 63/92頁(yè) |
| 文件大?。?/td> | 299K |
| 代理商： | LAN83C175 |
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63
15 through 1: Return zeroes to indicate that
64 Kbytes of address space are required.
1 - ADDRESS DECODE ENABLE: Controls
whether or not the LAN83C175 accepts
accesses to its expansion ROM.
3C - BUS REQUIREMENTS / INTERRUPT
MAP
Reset Value:
000000000000000000000001xxxxxxxx
31 through 24 - MAXIMUM LATENCY: This
read only field specifies how often the
LAN83C175 needs to gain access to the
CardBus bus.* To enable performance
tuning, the value is recalled from EEPROM
after reset.
23 through 16 - MINIMUM GRANT: This read
only field specifies how long a burst period the
LAN83C175 needs assuming a 33MHz
CardBus clock rate.* To enable performance
tuning, the value is recalled from
EEPROM after reset.
15 through 8 - INTERRUPT PIN: This read only
field returns 01h to indicate that the
LAN83C175's interrupt output is connected to the
nINTA pin on the CardBus connector.
7 through 0 - INTERRUPT LINE: This byte is
programmed with interrupt routing information.
The value indicates which input of the systems
interrupt controller(s) the LAN83C175's interrupt
pin is connected to. Values in this register are
system architecture specific.
* The maximum latency and minimum grant
registers are used to indicate the LAN83C175's
desired settings for Latency Timer values. Both
registers specify a period of time in units of 1/4
microsecond. For example, if the LAN83C175
needs to perform a burst 2 microseconds in length
every 11 microseconds (on the average), then the
maximum latency register would read 44 (1Ch)
and the minimum grant register would read 8
(08h).
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