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參數(shù)資料
| 型號： | LAN83C175 |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Ethernet CARDBUS Integrated Controller With Modem Support |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, TQFP-208 |
| 文件頁數(shù)： | 48/92頁 |
| 文件大?。?/td> | 299K |
| 代理商： | LAN83C175 |
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48
The receive status register reports the status
of the most-recently received packet. It
reports receive errors and address recognition
type. All bits are cleared at the start of
reception except for receiver disabled. The
contents of the lower order bits in this register
([6:0]) make up the lower order bits of the
receive packet stamp in the receive buffer.
31 through 7 - Unused.
6 - RECEIVER DISABLED: This bit is set
when the receiver is in monitor mode.
5 - BROADCAST ADDRESS RECOGNIZED:
This bit is set when a broadcast address has
been recognized.
4 - MULTICAST ADDRESS RECOGNIZED:
This bit is set when a multicast address which
passes the hash filter has been recognized.
3 - MISSED PACKET: This bit is set when a
packet with a recognized address and without
errors (or with masked errors) is not buffered
because the device is in monitor mode. This
bit is also set when the packet overflows the
receive buffer space and cannot be received.
Always returns 0.
2 - CRC ERROR: This bit is set when a
frame’s computed CRC does not match the
CRC appended to the frame. If the frame is a
runt, this bit will be clear. In MII mode, this bit
will also be set if receive error was asserted on
the MII interface during reception of the frame.
1 - FRAME ALIGNMENT ERROR: This bit is
set if a CRC error has occurred and the frame
is not byte aligned.
0 - PACKET RECEIVED INTACT: This bit is
set when a packet is received into the buffer
space without error.
68 - RECEIVE BYTE COUNT
Reset Value: 0000000000000000
This 16 bit register contains the receive byte count
for the most recently received frame. It is cleared
by the receive unit at the start of reception of each
frame.
5-0 - RECEIVE BYTE COUNT: D15 is the MSB
and D0 is the LSB.
6C - RECEIVE TEST
Reset Value: 00000xx00000000
31 through 15 - Unused.
14 through 10 - RECEIVE FIFO LEVEL: This 5
bit value returns the receive fifo level.
9 and 8 - Unused.
7 - RUNT STATUS: Returns 0 when the current
reception is not a runt or receive runt frames is
set. Returns zero when the current receive byte
count is less than the runt size. This bit is read
only.
6 through 0 - Reserved: Do not write ‘1’ to these
bits.
These bits are not readable and return unknown
data when read.
70 - TRANSMIT CONTROL
Reset Value: 01111000
31 through 8: Unused.
7 through 3 - SLOT TIME: Selects the number of
bit times to use for the slot time. The value
programmed plus one is multiplied by 32 to
generate the slot time. This value is used for both
the backoff timer and for runt checking. Default is
0Fh which gives a slot time of 512 bit times.
2 and 1 - LOOPBACK MODE SELECT:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LAN83C175TQFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMC Corporation of America 功能描述:83C175TQFP 制造商:SMSC 功能描述: |
| LAN83C175TQFP WAF | 制造商:SMSC 功能描述: |
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| LAN83C180_01 | 制造商:SMSC 制造商全稱:SMSC 功能描述:10/100 Fast Ethernet PHY Transceiver |
| LAN83C180TQFP | 制造商:SMSC 制造商全稱:SMSC 功能描述:10/100 Fast Ethernet PHY Transceiver |
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