L64005 MPEG-2 Audio/Video Decoder Technical Manual
4-11
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
The channel buffer controller uses these values to set the wrap-around
of front and back of buffer pointers. The channel buffer memory must be
contiguous. Changing the start and end pointer register during normal
operation is undened and not recommended.
If either the audio or video channel buffer becomes empty, the L64005
ags an error and may signal an interrupt. The audio and video decoders
stop when their respective channel buffers are empty. Channel buffer
underow results in a freeze frame (if the user issues a freeze frame) or
muted audio from the viewers perspective. Channel buffer underow may
occur in the middle of an MPEG symbol. This incomplete symbol may be
decoded incorrectly and may result in a channel or decode error.
The channel buffer is considered full when the main DRAM channel
buffer is full. Data in the on-chip read or write FIFOs is not considered
when determining the buffer full state. If the channel buffer becomes full,
the L64005 ags an error and may signal an interrupt. It also stops
asserting VREQ and AREQ. Data sent to the decoder at this time will be
lost, which results in decode errors and error concealment. The L64005
does not begin to add data to the channel buffers until the channel buff-
ers are no longer full.
Data in the elementary stream buffers is read automatically while the
decoder is playing. The external controller must explicitly read the Audio
and Video PES Header buffers to access the system header data. Data
can be held indenitely in the system stream buffers without being read.
However, data is overwritten eventually if it is not read while the decoder
is in system mode. The state of the AREQ and VREQ pins are always
controlled by the status of the Audio and Video Elementary stream buff-
ers regardless of the fullness of the system buffers. Users interested in
the system data should make sure that the system buffers are set large
enough, or that data is read out of them quickly enough. The audio and
video PES header buffers can be reset after the data has been read out
of DRAM.
4.3.2
User Data
Buffer
User data may be read through the system controller port when the data
is available. A small on-chip User Data FIFO allows the system controller
to respond to an interrupt that indicates that user data is available. User
data is parsed from the bitstream after reading the data from the channel
buffer.