
2-62
Registers
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
Register 34 contains the Video Channel Buffer Write Address
Register 35 contains the Audio Channel Buffer Write Address
Register 36 contains the Video Channel Buffer Read Address
Register 37 contains the Audio Channel Buffer Read Address
Register 38 contains the NSB of the previously read pointer
Register 39 contains the MSB of the previously read register
2.9.23
Group 7
Picture Start
Code Read
Address
Registers 40 through 42 hold the value of the video channel buffer
pointer registered at the time that a picture start code is decoded from
the bitstream out of the channel buffer. It contains the 18-bit internal
address as well as four MSBs to indicate the number of times the chan-
nel has rolled over the top of the FIFO. This value is generally 48 greater
than the actual Picture Start Code address in the channel because of the
delay caused by internal buffering. These registers are read only.
2.9.24
Group 7
Audio Sync
Code Read
Address
Registers 44 through 46 hold the value of the audio channel buffer
pointer registered at the time that an audio sync code is decoded from
the bitstream out of the channel buffer. It contains the 18-bit internal
address as well as four MSBs to indicate the number of times the chan-
nel has rolled over the top of the FIFO. This value is generally eight
greater than the actual Audio Start Code address in the channel because
of the delay caused by the internal buffering. These registers are read
only.
2.9.25
Group 7
Reserved
Registers
Registers 43 and 47 are reserved for LSI Logic use and should not be
read or written.
70
RESERVED
Register 43
70
RESERVED
Register 47