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參數(shù)資料
| 型號(hào)： | L64005-F |
| 廠商： | LSI CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 151/272頁(yè) |
| 文件大?。?/td> | 1252K |
| 代理商： | L64005-F |
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8-26
System Stream Decoding and Synchronization
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
8.5.4
Vertical Sync
Interrupt
The display controller generates a vertical sync interrupt that indicates
the presentation time of the eld. The presentation time is measured by
sampling the value of the SCR when the interrupt is generated. The SCR
is initialized with the value from the PCR clock recovery or optionally can
be initialized from an ESCR value from the PES packet. The SCR starts
to run on the L64005 27-MHz clock that, divided internally by 300, pro-
vides a 90-kHz input clock. From this point, the SCR value provides a
presentation time as a reference for comparison with all subsequent
PTSs obtained from the bitstream. After the initialization, the external
host processor compares the actual presentation time sampled from the
SCR against the expected PTS fetched from the PTS table. The external
host processor computes the differences between the expected and the
actual PTS, and commands a skip or repeat frame, if necessary, to retain
synchronization.
To provide a frame periodic synchronization monitor that is activated at
the beginning of actual presentation, only a top eld vertical sync inter-
rupt should be used to indicate the presentation time of the eld.
8.5.5
Audio Sync
Interrupt
Synchronizing audio is very similar to synchronizing video. The main dif-
ference is that for audio frames, the presentation order is the same as
the encoded order. The audio frame presentation time is very close to
the decode time. However, some xed delay time must be considered.
The audio decoder generates an audio sync interrupt each time an audio
frame starts decoding. The external host processor samples the Audio
Sync Code Read Address (Group 7, Registers 44-46) and associates
this value with the write pointer and PTS tables as shown in Figure 8.14.
A xed 8-word difference may be subtracted from the sync code address
to compensate for the internal channel FIFO size. Once PTS has been
identied, this PTS is used to compare the actual presentation time
against the expected PTS. The actual presentation time is sampled from
the SCR. The decode delay is dened as the time from when the audio
decoder starts decoding a new frame to the time that the decoder out-
puts the audio data. The decode delay is approximately 300 PCM sam-
ples—about 6.25 ms at 48 kHz, and should be added to the PTS prior
to comparison. If the difference between the expected PTS and actual
PTS is greater than one audio frame time—24 ms at 48 kHz in Layer 2,
skip whole frames or pause for an appropriate length of time to adjust
the output. For PTS differences less than one frame but greater than 2
ms, use the built-in skip and repeat functions to adjust the audio output
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| L64014A | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| L64010ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
| L64010ADCC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
| L64010ADM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
| L64010ADMB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
| L64010ADMC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Multiplier/Accumulator |
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