
vi
Preface
Final Rev F
Copyright 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
Pin 64 is CAS for the L64005, not BA9 (BA9 has been removed).
For Rev. E and F devices Pin 69 is now not connected (NC) and no
external loop lter is required. The lter may be left in place on any
board that already has it designed in.
For the L64005 Rev. D, Pin 69 is LP2. Regardless of the DRAM
mode used, an external loop lter must be included in the design
(requires one resistor and two capacitors for an off-chip loop lter).
The DRAM interface now supports both regular and synchronous
DRAM modes. See Section 5.3.2, “Synchronous DRAM Mode,” for
more information on the SDRAM interface.
New AC timing specications and drawings have been added to Sec-
tion 9.1
Pin 68 is Analog VDD (AVDD), and pin 70 is Analog GND (AGND).
These pins must be isolated from other VDD and VSS pins.
Please note that the L64005 has an on-chip PLL, so the 27-MHz
input clock must have low jitter (<300ps).
The duty cycle for SYSCLK has been specied slightly differently.
Please refer to Chapter 9, Specications, for details.
Software
Changes
A few changes must be made to L64005 supporting software.
Bit 0in Group 7, Register 27 must be set for reduced memory mode
(1=RMM, 0=Normal).
If reduced memory mode is used, Group 7, Register 27, Bits [7:2]
must be set to determine the number of 8-line segments used for a
B-frame decode.
Bits [4:3] of Group 7, Register 1 are no longer used for PMCT (1CAS
enable) or 512-page size select. In the L64005, bits [4:3] are used
to select the DRAM mode. Refer to Chapter 2 for more details.
In the L64005 32-bit mode is not supported. Bit 5 of Group 7, Reg-
ister 1 is now reserved.
Bit 6 of Group 7, Register 26 controls line doubling for the interlaced
display mode.
In the L64005, bits [7:0] in Group 7, Register 28 contains the hori-
zontal word origin of the luma and the chroma.