
L64005 MPEG-2 Audio/Video Decoder Technical Manual
2-33
Final Rev F
Copyright 1996 by LSI Logic Corporation. All rights reserved.
PDB
Pulldown from Bitstream
2, R/W
Setting PDB causes the L64005 to decode pulldown con-
trol from the MPEG-2 syntax in the bitstream. Clearing
PDB allows the user to control the pulldown.
FFLD
Freeze Field
1, R/W
Setting FLD freezes the current eld being displayed.
this bit should remain set for an even number of eld
times.
FFRM
Freeze Frame
0, R/W
Setting FFRM freezes the current frame displayed. See
bit should be set during the time in which the odd eld of
the frame to be frozen is being displayed, and remain set
for an even number of eld times. The decoder is auto-
matically stopped during the time when the frame is fro-
zen.
2.8.18
Group 6
Display Mode 1
Register 29 sets various options in the display controller. This register is
read/write.
REI
Reconstruction Error Indicator (Reserved)
7, R/W
This bit is reserved. During internal testing this bit is set
if a reconstructiuon error occurs while displaying a B Pic-
ture in Reduced Memory Mode. Refer to ECN Item 5.1.
MSAR
Memory Segment Allocator Reset (Reserved) 6, R/W
This bit is reserved. During internal testing, if the B Pic-
ture memory allocation unit becomes corrupted, setting
this bit would reset the allocator. Refer to ECN Item 5.1
PSB
Pan and Scan from Bitstream
5, R/W
Setting PSB causes the L64005 to decode the pan and
scan parameter from the bitstream. Clearing PSB allows
the user to set the pan and scan offsets through host
software control.
7
6
5
43210
REI
MSAR PSB
DMODE[2:0]
HFS
HFE
Register 29