參數(shù)資料
型號: KM4132G512
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256K x 32Bit x 2 Banks Synchronous Graphic RAM(256K x 32位 x 2組同步圖形 RAM)
中文描述: 256 × 32Bit的× 2銀行同步圖形存儲器(256K × 32位× 2組同步圖形RAM)的
文件頁數(shù): 7/49頁
文件大?。?/td> 934K
代理商: KM4132G512
KM4132G512
CMOS SGRAM
- 8 -
Rev. 2.2 (June 1998)
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-6
-7
-8
-10
Row active to row active delay
t
RRD(min)
12
14
16
20
ns
1
RAS to CAS delay
t
RCD(min)
16
16
16
20
ns
1
Row precharge time
t
RP(min)
18
21
24
26
ns
1
Row active time
t
RAS(min)
48
49
48
50
ns
1
t
RAS(max)
100
us
Row cycle time
t
RC(min)
66
70
72
78
ns
1
Last data in to new col. address delay
t
CDL(min)
1
CLK
2
Last data in to row precharge
t
RDL(min)
1
CLK
2
Last data in to burst stop
t
BDL(min)
1
CLK
2
Col. address to col. address delay
t
CCD(min)
1
CLK
3
Block write data-in to PRE command
t
BPL(min)
1
CLK
Block write cycle time
t
BWC(min)
1
CLK
1, 3
Number of valid output
data
CAS latency=3
2
CLK
4
CAS latency=2
1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Note :
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