參數(shù)資料
型號: ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機控制器
文件頁數(shù): 74/98頁
文件大小: 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
74 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.3.7
CONFIGFLAG register
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in
Table 104
.
[1]
The reserved bits should always be written with the reset value.
11.3.8
PORTSC registers 1, 2
The Port Status and Control (PORTSC) register is in the auxiliary power well. It is only
reset by hardware when the auxiliary power is initially applied or in response to a Host
Controller reset. The initial conditions of a port are:
Table 103: ASYNCLISTADDR - Current Asynchronous List Address register bit description
Address: Value read from func2 of address 10h + 38h
Bit
Symbol
Description
31 to 12
LPL[19:0]
Link Pointer List
: These bits correspond to memory address signals
31 to 12, respectively. This field may only reference a Queue Head (QH).
11 to 0
reserved
-
Table 104: CONFIGFLAG - Configure Flag register bit allocation
Address: Value read from func2 of address 10h + 60h
Bit
31
30
Symbol
Reset
0
0
Access
R/W
R/W
Bit
23
22
Symbol
Reset
0
0
Access
R/W
R/W
Bit
15
14
Symbol
Reset
0
0
Access
R/W
R/W
Bit
7
6
Symbol
Reset
0
0
Access
R/W
R/W
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
0
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
CF
0
R/W
reserved
[1]
0
R/W
0
0
0
0
R/W
R/W
R/W
R/W
Table 105: CONFIGFLAG - Configure Flag register bit description
Address: Value read from func2 of address 10h + 60h
Bit
Symbol
Description
31 to 1
reserved
-
0
CF
Configure Flag
: The host software sets this bit as the last action in its
process of configuring the Host Controller. This bit controls the default
port-routing control logic.
0 —
Port routing control logic default-routes each port to an implementation
dependent classic Host Controller
1 —
Port routing control logic default-routes all ports to this Host Controller.
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