參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁(yè)數(shù): 42/98頁(yè)
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
42 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.1.6
HcInterruptDisable register
Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the
HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the
corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this
register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a
read, the current value of the HcInterruptEnable register is returned.
The register contains 4 B, and the bit allocation is given in
Table 52
.
6
RHSC
Root Hub Status Change
:
0 —
Ignore
1 —
Enables interrupt generation because of Root Hub Status Change.
Frame Number Overflow
:
0 —
Ignore
1 —
Enables interrupt generation because of Frame Number Overflow.
Unrecoverable Error
:
0 —
Ignore
1 —
Enables interrupt generation because of Unrecoverable Error.
Resume Detect
:
0 —
Ignore
1 —
Enables interrupt generation because of Resume Detect.
Start-of-Frame
:
0 —
Ignore
1 —
Enables interrupt generation because of Start-of-Frame.
HcDoneHead Writeback
:
0 —
Ignore
1 —
Enables interrupt generation because of HcDoneHead Writeback.
Scheduling Overrun
:
0 —
Ignore
1 —
Enables interrupt generation because of Scheduling Overrun.
5
FNO
4
UE
3
RD
2
SF
1
WDH
0
SO
Table 51:
HcInterruptEnable - Host Controller Interrupt Enable register bit
description
…continued
Symbol
Description
Bit
Table 52:
Address: Value read from func0 or func1 of address 10h + 14h
Bit
31
Symbol
MIE
Reset
0
Access
R/W
Bit
23
Symbol
Reset
0
Access
R/W
HcInterruptDisable - Host Controller Interrupt Disable register bit allocation
30
OC
0
R/W
22
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
相關(guān)PDF資料
PDF描述
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
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