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參數(shù)資料
| 型號： | ISP1562 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus PCI Host Controller |
| 中文描述： | 高速通用串行總線PCI主機控制器 |
| 文件頁數(shù)： | 18/98頁 |
| 文件大小： | 442K |
| 代理商： | ISP1562 |
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9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
18 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8.2.1.5
Revision ID register
This 1 B read-only register indicates a device-specific revision identifier. The value is
chosen by the vendor. This field is a vendor-defined extension of the Device ID. The
Revision ID register bit description is given in
Table 10
.
8.2.1.6
Class Code register
Class Code is a 24-bit read-only register used to identify the generic function of the
device, and in some cases, a specific register-level programming interface.
Table 11
shows the bit allocation of the register.
10 to 9
DEVSELT
[1:0]
DEVSEL Timing
: These bits encode the timing of DEVSEL#. There are
three allowable timing to assert DEVSEL#:
00b —
Fast
01b —
Medium
10b —
Slow
11b —
Reserved.
These bits are read-only and must indicate the slowest time that a device
asserts DEVSEL# for any bus command, except Configuration Read and
Configuration Write.
Master Data Parity Error
: This bit is implemented by bus masters. It is set
when the following three conditions are met:
The bus agent asserted PERR# itself, on a read; or observed PERR#
asserted, on a write.
The agent setting the bit acted as the bus master for the operation in
which error occurred.
PER (bit 6 in the Command register) is set.
Fast Back-to-Back Capable
: This read-only bit indicates whether the
target is capable of accepting fast back-to-back transactions when the
transactions are not to the same agent. This bit can be set to logic 1, if the
device can accept these transactions; and must be set to logic 0 otherwise.
-
66 MHz Capable
: This read-only bit indicates whether this device is
capable of running at 66 MHz.
0 —
33 MHz
1 —
66 MHz.
Capabilities List
: This read-only bit indicates whether this device
implements the pointer for a new capabilities linked list at offset 34h.
0 —
No new capabilities linked list is available
1 —
The value read at offset 34h is a pointer in configuration space to a
linked list of new capabilities.
-
8
MDPE
7
FBBC
6
5
reserved
66MC
4
CL
3 to 0
reserved
Table 9:
Bit
Status register (address 06h) bit description
…continued
Symbol
Description
Table 10:
Legend: * reset value
Bit
Symbol
7 to 0
REVID[7:0]
REVID - Revision ID register (address 08h) bit description
Access
R
Value
11h*
Description
Revision ID
: This byte specifies the design revision
number of functions.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
| ISP1582 | Hi-Speed Universal Serial Bus peripheral controller |
| ISP1582BS | Hi-Speed Universal Serial Bus peripheral controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1562BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
| ISP1562BE,518 | 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BE,551 | 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BE,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BEGA | 功能描述:IC USB HOST CTRL HI-SPD 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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