參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁數(shù): 67/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
67 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.3.2
USBSTS register
The USB Status (USBSTS) register indicates pending interrupts and various states of the
Host Controller. The status resulting from a transaction on the serial bus is not indicated in
this register. Software clears the register bits by writing ones to them. The bit allocation is
given in
Table 94
.
5
ASE
Asynchronous Schedule Enable
: Default = 0. This bit controls whether
the Host Controller skips processing the asynchronous schedule.
0 —
Do not process the asynchronous schedule
1 —
Use the ASYNCLISTADDR register to access the asynchronous
schedule.
Periodic Schedule Enable
: Default = 0. This bit controls whether the
Host Controller skips processing the periodic schedule.
0 —
Do not process the periodic schedule
1 —
Use the PERIODICLISTBASE register to access the periodic
schedule.
Frame List Size
: Default = 00b. This field is read and write only if PFLF
(bit 1) in the HCCPARAMS register is set to logic 1. This field specifies the
size of the frame list. The size the frame list controls which bits in the
Frame Index register should be used for the frame list current index.
00b —
1024 elements (4096 B)
01b —
512 elements (2048 B)
10b —
256 elements (1024 B) for small environments
11b —
reserved.
HCRESET
Host Controller Reset
: This control bit is used by the software to reset
the Host Controller. The effects of this on Root Hub registers are similar to
a chip hardware reset. Setting this bit causes the Host Controller to reset
its internal pipelines, timers, counters, state machines, and so on, to their
initial values. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. This reset
does not affect the PCI Configuration registers. All operational registers,
including port registers and port state machines, are set to their initial
values. Port ownership reverts to the companion Host Controller(s). The
software must reinitialize the Host Controller to return it to an operational
state. This bit is cleared by the Host Controller when the reset process is
complete. Software cannot terminate the reset process early by writing
logic 0 to this register. Software should check that bit HCH is logic 0 before
setting this bit. Attempting to reset an actively running Host Controller
results in undefined behavior.
RS
Run/Stop
: 1 = Run. 0 = Stop. When set, the Host Controller executes the
schedule. The Host Controller continues execution as long as this bit is
set. When this bit is cleared, the Host Controller completes the current and
active transactions in the USB pipeline, and then halts. Bit HCH indicates
when the Host Controller has finished the transaction and has entered the
stopped state. Software should check that the HCH bit is logic 1, before
setting this bit.
4
PSE
3 to 2
FLS[1:0]
1
0
Table 93:
Address: Value read from func2 of address 10h + 20h
Bit
Symbol
Description
USBCMD - USB Command register bit description
…continued
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