參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁數(shù): 47/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
47 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.1.11
HcBulkHeadED register
This register (see
Table 62
) contains the physical address of the first ED of the bulk list.
[1]
The reserved bits should always be written with the reset value.
11.1.12
HcBulkCurrentED register
This register contains the physical address of the current endpoint of the bulk list. The
endpoints are ordered according to their insertion to the list because the bulk list must be
served in a round-robin fashion. The bit allocation is given in
Table 64
.
Table 62:
Address: Value read from func0 or func1 of address 10h + 28h
Bit
31
Symbol
Reset
0
Access
R/W
Bit
23
Symbol
Reset
0
Access
R/W
Bit
15
Symbol
Reset
0
Access
R/W
Bit
7
Symbol
Reset
0
Access
R/W
HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation
30
29
28
27
26
25
24
BHED[27:20]
0
R/W
20
BHED[19:12]
0
R/W
12
BHED[11:4]
0
R/W
4
0
0
0
0
0
0
R/W
22
R/W
21
R/W
19
R/W
18
R/W
17
R/W
16
0
0
0
0
0
0
R/W
14
R/W
13
R/W
11
R/W
10
R/W
9
R/W
8
0
0
0
0
0
0
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
BHED[3:0]
reserved
[1]
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 63:
HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit
description
Address: Value read from func0 or func1 of address 10h + 28h
Bit
Symbol
Description
31 to 4
BHED[27:0]
BulkHeadED
: The Host Controller traverses the bulk list starting with
the HcBulkHeadED pointer. The content is loaded from HCCA during
the initialization of the Host Controller.
3 to 0
reserved
-
Table 64:
Address: Value read from func0 or func1 of address 10h + 2Ch
Bit
31
Symbol
Reset
0
Access
R/W
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation
30
29
28
27
26
25
24
BCED[27:20]
0
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
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