參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁(yè)數(shù): 49/98頁(yè)
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
49 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
The reserved bits should always be written with the reset value.
11.1.14
HcFmInterval register
This register contains a 14-bit value that indicates the bit time interval in a frame—that is,
between two consecutive SOFs—and a 15-bit value indicating the full-speed maximum
packet size that the Host Controller may transmit or receive, without causing a scheduling
overrun. The HCD may carry out minor adjustment on FI (FrameInterval) by writing a new
value over the present at each SOF. This provides the possibility for the Host Controller to
synchronize with an external clocking resource and to adjust any unknown local clock
offset. The bit allocation of the register is given in
Table 68
.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15
14
13
12
11
10
9
8
DH[11:4]
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
DH[3:0]
reserved
[1]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 67:
Address: Value read from func0 or func1 of address 10h + 30h
Bit
Symbol
Description
31 to 4
DH[27:0]
DoneHead
: When a TD is completed, the Host Controller writes the
content of HcDoneHead to the NextTD field of the TD. The Host
Controller then overwrites the content of HcDoneHead with the
address of this TD. This is set to logic 0 whenever the Host Controller
writes the content of this register to HCCA.
3 to 0
reserved
-
HcDoneHead - Host Controller Done Head register bit description
Table 68:
Address: Value read from func0 or func1 of address 10h + 34h
Bit
31
Symbol
FIT
Reset
0
Access
R/W
Bit
23
Symbol
Reset
0
Access
R/W
Bit
15
Symbol
reserved
[1]
Reset
0
Access
R/W
HcFmInterval - Host Controller Frame Interval register bit allocation
30
29
28
27
26
25
24
FSMPS[14:8]
0
R/W
19
FSMPS[7:0]
0
0
0
0
0
0
R/W
22
R/W
21
R/W
20
R/W
18
R/W
17
R/W
16
0
0
0
0
0
0
0
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
FI[13:8]
0
1
0
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
相關(guān)PDF資料
PDF描述
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
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