參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁(yè)數(shù): 48/98頁(yè)
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
48 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
The reserved bits should always be written with the reset value.
11.1.13
HcDoneHead register
The HcDoneHead register contains the physical address of the last completed TD that
was added to the Done queue. In normal operation, the HCD need not read this register
because its content is periodically written to the HCCA.
Table 66
contains the bit allocation
of the register.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
23
22
21
20
19
18
17
16
BCED[19:12]
0
R/W
12
BCED[11:4]
0
R/W
4
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
11
R/W
10
R/W
9
R/W
8
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
BCED[3:0]
reserved
[1]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 65:
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit
description
Address: Value read from func0 or func1 of address 10h + 2Ch
Bit
Symbol
Description
31 to 4 BCED[27:0]
BulkCurrentED
: This is advanced to the next ED after the Host Controller
has served the current ED. The Host Controller continues processing the
list from where it left off in the last frame. When it reaches the end of the
bulk list, the Host Controller checks CLF (bit 1 of HcCommandStatus). If
the CLF bit is not set, nothing is done. If the CLF bit is set, it copies the
content of HcBulkHeadED to HcBulkCurrentED and clears the CLF bit.
The HCD can modify this register only when BLE (bit 5 in the HcControl
register) is cleared. When HcControl is set, the HCD reads the
instantaneous value of this register. This is initially set to logic 0 to indicate
the end of the bulk list.
3 to 0
reserved
-
Table 66:
Address: Value read from func0 or func1 of address 10h + 30h
Bit
31
Symbol
Reset
0
Access
R/W
Bit
23
Symbol
Reset
0
Access
R/W
HcDoneHead - Host Controller Done Head register bit allocation
30
29
28
27
26
25
24
DH[27:20]
0
0
0
0
0
0
0
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
DH[19:12]
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
相關(guān)PDF資料
PDF描述
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
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