參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁(yè)數(shù): 26/98頁(yè)
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
26 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8.2.3.3
PMC register
The Power Management Capabilities (PMC) register is a 2 B register, and the bit
allocation is given in
Table 33
. This register provides information on the capabilities of the
function related to power management.
[1]
X is 0 for OHCI1 and OHCI2; X is 1 for EHCI.
Table 32:
Address: Value read from address 34h + 1h
Legend: * reset value
Bit
Symbol
7 to 0
NEXT_ITEM_
PTR[7:0]
Next_Item_Ptr - Next Item Pointer register bit description
Access
R
Value
00h*
Description
Next Item Pointer
: This field provides an offset into
the function’s PCI configuration space, pointing to the
location of the next item in the function’s capability list.
If there are no additional items in the capabilities list,
this register is set to 00h.
Table 33:
Address: Value read from address 34h + 2h
Bit
15
Symbol
Reset
1
Access
R
Bit
7
Symbol
AUX_C[1:0]
Reset
1
Access
R
PMC - Power Management Capabilities register bit allocation
14
13
12
11
10
9
8
PME_S[4:0]
X
[1]
R
5
DSI
0
R
D2_S
X
[1]
R
2
D1_S
1
R
1
VER[2:0]
1
R
AUX_C
0
R
0
1
R
6
1
R
4
X
[1]
R
3
PMI
0
R
reserved
0
R
0
R
0
R
0
R
Table 34:
Address: Value read from address 34h + 2h
Bit
Symbol
Description
15 to 11 PME_S
[4:0]
may assert PME#. Logic 0 for any bit indicates that the function is not
capable of asserting the PME# signal while in that power state.
PME_S[0] —
PME# can be asserted from D0
PME_S[1] —
PME# can be asserted from D1
PME_S[2] —
PME# can be asserted from D2
PME_S[3] —
PME# can be asserted from D3
hot
PME_S[4] —
PME# can be asserted from D3
cold
.
10
D2_S
D2_Support
: If this bit is logic 1, this function supports the D2 Power
Management State. Functions that do not support D2 must always return
logic 0 for this bit.
9
D1_S
D1_Support
: If this bit is logic 1, this function supports the D1 Power
Management State. Functions that do not support D1 must always return
logic 0 for this bit.
PMC - Power Management Capabilities register bit description
PME_Support
: These bits indicate the power states in which the function
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