參數(shù)資料
型號: ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機控制器
文件頁數(shù): 72/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
72 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.3.5
PERIODICLISTBASE register
The Periodic Frame List Base Address (PERIODLISTBASE) register contains the
beginning address of the periodic frame list in the system memory. If the Host Controller is
in 64-bit mode—as indicated by logic 1 in 64AC (bit 0 of the HCCSPARAMS register)—the
most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register. The system software loads this register before starting the
schedule execution by the Host Controller. The memory structure referenced by this
physical memory pointer is assumed as 4 kB aligned. The contents of this register are
combined with the FRINDEX register to enable the Host Controller to step through the
periodic frame list in sequence.
The bit allocation is given in
Table 100
.
Table 99:
Address: Value read from func2 of address 10h + 2Ch
Bit
Symbol
Description
31 to 14
reserved
-
13 to 0
FRINDEX
[13:0]
packet and as the index into the frame list. The value in this register
increments at the end of each time frame. For example, micro frame. The
bits used for the frame number in the SOF token are taken from bits 13 to 3
of this register. Bits N to 3 are used for the frame list current index. This
means that each location of the frame list is accessed eight times—frames
or micro frames—before moving to the next index.
The following illustrates values of N based on the value of FLS[1:0]
(bits 3 to 2 in the USBCMD register).
FLS[1:0]
00b
01b
10b
11b
FRINDEX - Frame Index register bit description
Frame Index
: Bits in this register are used for the frame number in the SOF
Number elements
1024
512
256
reserved
N
12
11
10
-
Table 100: PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation
Address: Value read from func2 of address 10h + 34h
Bit
31
30
29
Symbol
Reset
0
0
0
Access
R/W
R/W
R/W
Bit
23
22
21
Symbol
Reset
0
0
0
Access
R/W
R/W
R/W
Bit
15
14
13
Symbol
BA[3:0]
Reset
0
0
0
Access
R/W
R/W
R/W
28
27
26
25
24
BA[19:12]
0
0
0
0
0
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
BA[11:4]
0
0
0
0
0
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
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