參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁數(shù): 46/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
46 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.1.10
HcControlCurrentED register
The HcControlCurrentED register contains the physical address of the current ED of the
control list. The bit allocation is given in
Table 60
.
Table 59:
HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit
description
Address: Value read from func0 or func1 of address 10h + 20h
Bit
Symbol
Description
31 to 4
CHED[27:0]
ControlHeadED
: The Host Controller traverses the control list, starting
with the HcControlHeadED pointer. The content is loaded from HCCA
during the initialization of the Host Controller.
3 to 0
reserved
-
Table 60:
Address: Value read from func0 or func1 of address 10h + 24h
Bit
31
Symbol
Reset
0
Access
R
Bit
23
Symbol
Reset
0
Access
R
Bit
15
Symbol
Reset
0
Access
R
Bit
7
Symbol
Reset
0
Access
R
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation
30
29
28
27
26
25
24
CCED[27:20]
0
R
20
CCED[19:12]
0
R
12
CCED[11:4]
0
R
4
0
R
22
0
R
21
0
R
19
0
R
18
0
R
17
0
R
16
0
R
14
0
R
13
0
R
11
0
R
10
0
R
9
0
R
8
0
R
6
0
R
5
0
R
3
0
R
2
0
R
1
0
R
0
CCED[3:0]
reserved
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Table 61:
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor
register bit description
Address: Value read from func0 or func1 of address 10h + 24h
Bit
Symbol
Description
31 to 4
CCED[27:0]
ControlCurrentED
: This pointer is advanced to the next ED after serving
the present. The Host Controller must continue processing the list from
where it left off in the last frame. When it reaches the end of the control list,
the Host Controller checks CLF (bit 1 of HcCommandStatus). If set, it
copies the content of HcControlHeadED to HcControlCurrentED and
clears the bit. If not set, it does nothing. The HCD is allowed to modify this
register only when CLE (bit 4 in the HcControl register) is cleared. When
set, the HCD only reads the instantaneous value of this register. Initially,
this is set to logic 0 to indicate the end of the control list.
3 to 0
reserved
-
相關(guān)PDF資料
PDF描述
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