參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁(yè)數(shù): 50/98頁(yè)
文件大小: 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
50 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
The reserved bits should always be written with the reset value.
11.1.15
HcFmRemaining register
This register is a 14-bit down counter showing the bit time remaining in the current frame.
Table 70
contains the bit allocation of this register.
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
FI[7:0]
1
1
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 69:
Address: Value read from func0 or func1 of address 10h + 34h
Bit
Symbol
Description
31
FIT
FrameIntervalToggle
: The HCD toggles this bit whenever it loads a
new value to FrameInterval.
30 to 16
FSMPS[14:0]
FSLargestDataPacket
: This field specifies the value that is loaded
into the largest data packet counter at the beginning of each frame.
The counter value represents the largest amount of data in bits that
can be sent or received by the Host Controller in a single transaction at
any given time, without causing a scheduling overrun. The field value
is calculated by the HCD.
15 to 14
reserved
-
13 to 0
FI[13:0]
FrameInterval
: This specifies the interval between two consecutive
SOFs in bit times. The nominal value is set to 11,999. The HCD should
store the current value of this field before resetting the Host Controller
to reset this field to its nominal value. The HCD can then restore the
stored value on completing the reset sequence.
HcFmInterval - Host Controller Frame Interval register bit description
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