參數(shù)資料
型號： HYB18L128160BF-75
廠商： INFINEON TECHNOLOGIES AG
英文描述： ECONOLINE: RKZ - Safety standards and approvals: EN 60950 certified, rated for 250VAC (LVD test report)- Custom Solutions Available- 3kVDC & 4kVDC Isolation- UL94V-0 Package Material- Power Sharing on Output- Efficiency to 84%
中文描述： 針對移動應用的DRAM
文件頁數(shù)： 31/53頁
文件大?。?/td> 1328K
代理商： HYB18L128160BF-75
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Data Sheet
31
V1.4, 2004-04-30
Figure 25
WRITE Burst (CAS Latency = 2)
Figure 26
WRITE Burst (CAS Latency = 3)
Table 11
Parameter
Timing Parameters for WRITE
Symbol
- 7.5
Units
Notes
min.
1.5
0.8
0
67
19
45
14
19
max.
–
–
–
–
–
100k
–
–
DQ and DQM input setup time
DQ and DQM input hold time
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
t
IS
t
IH
ns
ns
t
CK
ns
ns
ns
ns
ns
–
–
–
1)
t
DQW
t
RC
t
RCD
t
RAS
t
WR
t
RP
1)
1)
1)
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
= Don't Care
CLK
t
RCD
t
RAS
t
RC
t
RP
t
WR
Command
NOP
WRITE
NOP
NOP
NOP
PRE
NOP
ACT
ACT
NOP
Address
Ba A,
Row x
Ba A,
Col n
Ba A,
Row b
Row x
Row b
Dis
AP
AP
Pre Bank A
Pre All
A10 (AP)
DQ
DI n
DI n+2
DI n+3
DI n+1
Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
= Don't Care
t
RCD
t
RAS
t
RC
t
RP
t
WR
CLK
Command
NOP
WRITE
NOP
NOP
NOP
PRE
NOP
ACT
ACT
NOP
NOP
NOP
Address
Ba A,
Row n
Ba A,
Col n
Ba A,
Row b
Pre Bank A
Pre All
Row
x
Dis
AP
AP
Row
b
A10 (AP)
DQ
DI n
DI n+2
DI n+3
DI n+1
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