參數(shù)資料
型號(hào)： HYB18L128160BF-75
廠商： INFINEON TECHNOLOGIES AG
英文描述： ECONOLINE: RKZ - Safety standards and approvals: EN 60950 certified, rated for 250VAC (LVD test report)- Custom Solutions Available- 3kVDC & 4kVDC Isolation- UL94V-0 Package Material- Power Sharing on Output- Efficiency to 84%
中文描述： 針對(duì)移動(dòng)應(yīng)用的DRAM
文件頁(yè)數(shù)： 10/53頁(yè)
文件大?。?/td> 1328K
代理商： HYB18L128160BF-75
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Overview
Data Sheet
10
V1.4, 2004-04-30
1.4
Pin Definition and Description
Table 4
Ball
CLK
CKE
Pin Description
Type
Input
Input
Detailed Function
Clock:
all inputs are sampled on the positive edge of CLK.
Clock Enable:
CKE HIGH activates and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-
DOWN (row active in any bank) or SUSPEND (access in progress). Input buffers,
excluding CLK and CKE are disabled during power-down. Input buffers, excluding CKE
are disabled during SELF REFRESH.
Chip Select:
All commands are masked when CS is registered HIGH. CS provides for
external bank selection on systems with multiple memory banks. CS is considered part of
the command code.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being
entered.
Data Inputs/Output:
Bi-directional data bus (16 bit)
Input/Output Mask:
input mask signal for WRITE cycles and output enable for READ
cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as
an output enable and places the output buffers in High-Z state when HIGH (two clocks
latency).
LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15.
Bank Address Inputs:
BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE
or PRECHARGE command is being applied. BA0, BA1 also determine which mode
register is to be loaded during a MODE REGISTER SET command (MRS or EMRS).
Address Inputs:
A0 - A11 define the row address during an ACTIVE command cycle. A0
- A8 define the column address during a READ or WRITE command cycle. In addition,
A10 (= AP) controls Auto Precharge operation at the end of the burst read or write cycle.
During a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls
which bank(s) are to be precharged: if A10 is HIGH, all four banks will be precharged
regardless of the state of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be
precharged. During MODE REGISTER SET commands, the address inputs hold the op-
code to be loaded.
Supply
I/O Power Supply:
Isolated power for DQ output buffers for improved noise immunity:
V
DDQ
= 1.8 V
±
0.15 V
Supply
I/O Ground
Supply
Power Supply:
Power for the core logic and input buffers,
V
DD
= 1.8 V
±
0.15 V
Supply
Ground
–
No Connect
CS
Input
RAS, CAS,
WE
DQ0 - DQ15
LDQM,
UDQM
Input
I/O
Input
BA0, BA1
Input
A0 - A11
Input
V
DDQ
V
SSQ
V
DD
V
SS
N.C.
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