參數(shù)資料
型號: HYB18L128160BF-75
廠商: INFINEON TECHNOLOGIES AG
英文描述: ECONOLINE: RKZ - Safety standards and approvals: EN 60950 certified, rated for 250VAC (LVD test report)- Custom Solutions Available- 3kVDC & 4kVDC Isolation- UL94V-0 Package Material- Power Sharing on Output- Efficiency to 84%
中文描述: 針對移動應(yīng)用的DRAM
文件頁數(shù): 29/53頁
文件大?。?/td> 1328K
代理商: HYB18L128160BF-75
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional Description
Data Sheet
29
V1.4, 2004-04-30
2.4.6
WRITE
Figure 23
WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in
Figure 23
. Basic timings for the DQs are shown
in
Figure 24
; they apply to all write operations.
The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
completion of the write burst. For the generic WRITE commands used in the following illustrations, Auto Precharge
is disabled.
Figure 24
Basic WRITE Timing Parameters for DQs
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored.
Figure 25
and
Figure 26
show a single WRITE burst for each supported CAS latency setting.
BA0,BA1
BA
CS
CKE
(High)
CLK
RAS
CAS
A0-A8
CA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
A10
AP
Disable AP
Enable AP
WE
CLK
= Don't Care
t
IS
t
IH
t
IS
t
IH
DQM
DQ
DI n
DI n+2
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