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(5) Timer A to C Interrupt Request Flags (IFTA: $001, 2*, IFTB: $002, 0, IFTC: $002, 2):
IFTA to IFTC are flags that reflect whether an interrupt request is outstanding from the
corresponding timer A to C. When one of timers A to C overflows, the corresponding interrupt
request flag (IFTA to IFTC) is set to 1.
IFTA to IFTC can be read and written only by the bit manipulation instructions.
However, note that only a 0 may be written.
IFTA to IFTC are never cleared automatically, even when an interrupt is received. They must be
cleared to 0 by the software.
These flags are cleared to 0 on reset and in stop mode.
IFTA* to IFTC
Description
0
Indicates that no interrupt has been requested by the corresponding timer
A to C.
(initial value)
1
Indicates that an interrupt has been requested by the corresponding timer
A to C.
Note: * The timer A interrupt request flag (IFTA) applies to the HD404318, HD404358,
HD404358R, HD404339, and HD404369 Series. Since there is no timer A in HD404344R
and HD404394 Series products, the IFTA flag cannot be used in those products.
(6) Timer A to C Interrupt Masks (IMTA: $001, 3*, IMTB: $002, 1, IMTC: 002, 3): IMTA
to IMTC are bits that mask the corresponding IFTA to IFTC flags. The CPU will accept a timer
interrupt when one of IFTA to IFTC is set to 1 only if the corresponding IMTA to IMTC is cleared
to 0 and IE is 1.
if IMTA to IMTC is set to 1, even if the corresponding IFTA or IFTC is set to 1. That is, the
interrupt will be deferred.
IMTA to IMTC can be read and written only by the bit manipulation instructions.
These masks are set to 1 on reset and in stop mode.
IMTA* to IMTC
Description
0
IFTA to IFTC are enabled.
1
IFTA to IFTC are masked. The interrupt will be deferred even if any of IFTA to
IFTC are set to 1.
(initial value)
Note: * The timer A interrupt mask (IMTA) applies to the HD404318, HD404358, HD404358R,
HD404339, and HD404369 Series. Since there is no timer A in HD404344R and HD404394
Series products, the IMTA mask cannot be used in those products.