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Section 14 Oscillator Circuits
(HD404339 and HD404369 Series)
14.1
Overview
14.1.1
Features
The microcomputers in the HD404339 and HD404369 Series include a system clock oscillator
circuit and a subsystem clock oscillator circuit with the following features.
The system clock oscillator circuit supports the use of a ceramic or crystal oscillator or an
external clock input. The system clock is generated by dividing the oscillator frequency by
either 4, 8, 16, or 32 internally (i.e., f
cyc = fOSC/4, fOSC/8, fOSC/16, or fOSC/32: the divisor is
software selectable). Note that
CPU = PER = fcyc.
The following oscillator elements and external clock frequencies can be used.
HD404339 Series
Use an oscillator element or an external clock with a frequency in the range 0.4 to 4.5 MHz.
HD404369 Series
Use an oscillator element or an external clock with a frequency in either the range 0.4 to 5.0
MHz*
1, or the range 0.4 to 8.5 MHz*2.
Notes: 1. HD404364, HD404368, HD4043612, HD404369
2. HD40A4364, HD40A4368, HD40A43612, HD40A4369, HD407A4369
The built-in peripheral module operating clock (
PER) is input to an 11-bit prescaler (PSS) and
divided to generate the clocks that are used as the counter operating clocks for the built-in
peripheral modules. The divisors can be set individually using the mode registers for each
built-in peripheral module.
A 32.768 kHz crystal oscillator is used as the subsystem clock oscillator. A clock generated by
dividing this frequency by four or eight (f
SUB = fX/4 or fX/8) with an internal divider circuit is
used as the system clock in subactive mode. The divisor can be selected by setting a register.
In all operating modes, a clock generated by dividing the subsystem clock frequency by eight
is input to prescaler W (PSW). A clock generated by PSW division is used in timer A clock
time base operation.