
47
Figure 2-7 shows the RAM memory map for the microcomputers in the HD404369 Series.
W
R/W
W
R/W
W
R/W
W
R
W
Interrupt control bit area
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$016
$017
$018
$019
$01A
$020
$023
$024
$025
$026
$027
$028
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$039
(PMRA)
(SMR)
(SRL)
(SRU)
(TMA)
(TMB1)
(TRBL/TWBL)
(TRBU/TWBU)
(MIS)
(TMC)
(TRCL/TWCL)
(TRCU/TWCU)
$000
$03F
(ACR)
(ADRL)
(ADRU)
(AMR1)
(AMR2)
(PMRB)
(PMRC)
(TMB2)
(SSR1)
(SSR2)
(DCD0)
(DCD1)
(DCD2)
(DCD3)
(DCR0)
(DCR1)
(DCR2)
(DCR3)
(DCR4)
(DCR5)
(DCR6)
(DCR7)
(DCR8)
(DCR9)
*
$040
$050
$3C0
$3FF
$200
$00A
$00B
$00E
$00F
(TWBL)
(TWBU)
W
R
W
R
(TRBL)
(TRBU)
(TRCL)
(TRCU)
(TWCL)
(TWCU)
Symbols
R:
W:
R/W:
Read only
Write only
Read/Write
Note: * Two registers are mapped to the same address at locations $00A, $00B, $00E, and $00F.
RAM address
Unused
Register flag area
Unused
Port mode register A
Serial mode register
Serial data register L
Serial data register U
Timer mode register A
Timer mode register B1
Miscellaneous register
Timer mode register C
Timer B
Timer C
A/D channel register
A/D data register L
A/D data register U
A/D mode register 1
A/D mode register 2
Port mode register B
Port mode register C
Port mode register B2
System clock selection register 1
System clock selection register 2
Data control registers D0 to D3
Data control registers D4 to D7
Data control registers D8 to D11
Data control registers D12 and D13
Data control register R0
Data control register R1
Data control register R2
Data control register R3
Data control register R4
Data control register R5
Data control register R6
Data control register R7
Data control register R8
Data control register R9
Timer write register BL
Timer write register BU
Timer write register CL
Timer write register CU
Timer read register BL
Timer read register BU
Timer read register CL
Timer read register CU
RAM mapped
register area
Memory register (MR)
Data
(432 digits)
Unused
Stack
(64 digits)
Figure 2-7 HD404369 Series RAM Memory Map